M480 BSP
V3.05.006
The Board Support Package for M480 Series
Device
Nuvoton
M480
Include
emac_reg.h
Go to the documentation of this file.
1
/**************************************************************************/
9
#ifndef __EMAC_REG_H__
10
#define __EMAC_REG_H__
11
12
#if defined ( __CC_ARM )
13
#pragma anon_unions
14
#endif
15
26
typedef
struct
27
{
28
3073
__IO uint32_t
CAMCTL
;
3074
__IO uint32_t
CAMEN
;
3075
__IO uint32_t
CAM0M
;
3076
__IO uint32_t
CAM0L
;
3077
__IO uint32_t
CAM1M
;
3078
__IO uint32_t
CAM1L
;
3079
__IO uint32_t
CAM2M
;
3080
__IO uint32_t
CAM2L
;
3081
__IO uint32_t
CAM3M
;
3082
__IO uint32_t
CAM3L
;
3083
__IO uint32_t
CAM4M
;
3084
__IO uint32_t
CAM4L
;
3085
__IO uint32_t
CAM5M
;
3086
__IO uint32_t
CAM5L
;
3087
__IO uint32_t
CAM6M
;
3088
__IO uint32_t
CAM6L
;
3089
__IO uint32_t
CAM7M
;
3090
__IO uint32_t
CAM7L
;
3091
__IO uint32_t
CAM8M
;
3092
__IO uint32_t
CAM8L
;
3093
__IO uint32_t
CAM9M
;
3094
__IO uint32_t
CAM9L
;
3095
__IO uint32_t
CAM10M
;
3096
__IO uint32_t
CAM10L
;
3097
__IO uint32_t
CAM11M
;
3098
__IO uint32_t
CAM11L
;
3099
__IO uint32_t
CAM12M
;
3100
__IO uint32_t
CAM12L
;
3101
__IO uint32_t
CAM13M
;
3102
__IO uint32_t
CAM13L
;
3103
__IO uint32_t
CAM14M
;
3104
__IO uint32_t
CAM14L
;
3105
__IO uint32_t
CAM15MSB
;
3106
__IO uint32_t
CAM15LSB
;
3107
__IO uint32_t
TXDSA
;
3108
__IO uint32_t
RXDSA
;
3109
__IO uint32_t
CTL
;
3110
__IO uint32_t
MIIMDAT
;
3111
__IO uint32_t
MIIMCTL
;
3112
__IO uint32_t
FIFOCTL
;
3113
__O uint32_t
TXST
;
3114
__O uint32_t
RXST
;
3115
__IO uint32_t
MRFL
;
3116
__IO uint32_t
INTEN
;
3117
__IO uint32_t
INTSTS
;
3118
__IO uint32_t
GENSTS
;
3119
__IO uint32_t
MPCNT
;
3120
__I uint32_t
RPCNT
;
3122
__I uint32_t RESERVE0[2];
3124
__IO uint32_t
FRSTS
;
3125
__I uint32_t
CTXDSA
;
3126
__I uint32_t
CTXBSA
;
3127
__I uint32_t
CRXDSA
;
3128
__I uint32_t
CRXBSA
;
3130
__I uint32_t RESERVE1[9];
3132
__IO uint32_t
TSCTL
;
3134
__I uint32_t RESERVE2[3];
3136
__I uint32_t
TSSEC
;
3137
__I uint32_t
TSSUBSEC
;
3138
__IO uint32_t
TSINC
;
3139
__IO uint32_t
TSADDEND
;
3140
__IO uint32_t
UPDSEC
;
3141
__IO uint32_t
UPDSUBSEC
;
3142
__IO uint32_t
ALMSEC
;
3143
__IO uint32_t
ALMSUBSEC
;
3145
}
EMAC_T
;
3146
3152
#define EMAC_CAMCTL_AUP_Pos (0)
3153
#define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos)
3155
#define EMAC_CAMCTL_AMP_Pos (1)
3156
#define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos)
3158
#define EMAC_CAMCTL_ABP_Pos (2)
3159
#define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos)
3161
#define EMAC_CAMCTL_COMPEN_Pos (3)
3162
#define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos)
3164
#define EMAC_CAMCTL_CMPEN_Pos (4)
3165
#define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos)
3167
#define EMAC_CAMEN_CAMxEN_Pos (0)
3168
#define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos)
3170
#define EMAC_CAM0M_MACADDR2_Pos (0)
3171
#define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos)
3173
#define EMAC_CAM0M_MACADDR3_Pos (8)
3174
#define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos)
3176
#define EMAC_CAM0M_MACADDR4_Pos (16)
3177
#define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos)
3179
#define EMAC_CAM0M_MACADDR5_Pos (24)
3180
#define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos)
3182
#define EMAC_CAM0L_MACADDR0_Pos (16)
3183
#define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos)
3185
#define EMAC_CAM0L_MACADDR1_Pos (24)
3186
#define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos)
3188
#define EMAC_CAM1M_MACADDR2_Pos (0)
3189
#define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos)
3191
#define EMAC_CAM1M_MACADDR3_Pos (8)
3192
#define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos)
3194
#define EMAC_CAM1M_MACADDR4_Pos (16)
3195
#define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos)
3197
#define EMAC_CAM1M_MACADDR5_Pos (24)
3198
#define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos)
3200
#define EMAC_CAM1L_MACADDR0_Pos (16)
3201
#define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos)
3203
#define EMAC_CAM1L_MACADDR1_Pos (24)
3204
#define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos)
3206
#define EMAC_CAM2M_MACADDR2_Pos (0)
3207
#define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos)
3209
#define EMAC_CAM2M_MACADDR3_Pos (8)
3210
#define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos)
3212
#define EMAC_CAM2M_MACADDR4_Pos (16)
3213
#define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos)
3215
#define EMAC_CAM2M_MACADDR5_Pos (24)
3216
#define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos)
3218
#define EMAC_CAM2L_MACADDR0_Pos (16)
3219
#define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos)
3221
#define EMAC_CAM2L_MACADDR1_Pos (24)
3222
#define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos)
3224
#define EMAC_CAM3M_MACADDR2_Pos (0)
3225
#define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos)
3227
#define EMAC_CAM3M_MACADDR3_Pos (8)
3228
#define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos)
3230
#define EMAC_CAM3M_MACADDR4_Pos (16)
3231
#define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos)
3233
#define EMAC_CAM3M_MACADDR5_Pos (24)
3234
#define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos)
3236
#define EMAC_CAM3L_MACADDR0_Pos (16)
3237
#define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos)
3239
#define EMAC_CAM3L_MACADDR1_Pos (24)
3240
#define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos)
3242
#define EMAC_CAM4M_MACADDR2_Pos (0)
3243
#define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos)
3245
#define EMAC_CAM4M_MACADDR3_Pos (8)
3246
#define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos)
3248
#define EMAC_CAM4M_MACADDR4_Pos (16)
3249
#define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos)
3251
#define EMAC_CAM4M_MACADDR5_Pos (24)
3252
#define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos)
3254
#define EMAC_CAM4L_MACADDR0_Pos (16)
3255
#define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos)
3257
#define EMAC_CAM4L_MACADDR1_Pos (24)
3258
#define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos)
3260
#define EMAC_CAM5M_MACADDR2_Pos (0)
3261
#define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos)
3263
#define EMAC_CAM5M_MACADDR3_Pos (8)
3264
#define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos)
3266
#define EMAC_CAM5M_MACADDR4_Pos (16)
3267
#define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos)
3269
#define EMAC_CAM5M_MACADDR5_Pos (24)
3270
#define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos)
3272
#define EMAC_CAM5L_MACADDR0_Pos (16)
3273
#define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos)
3275
#define EMAC_CAM5L_MACADDR1_Pos (24)
3276
#define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos)
3278
#define EMAC_CAM6M_MACADDR2_Pos (0)
3279
#define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos)
3281
#define EMAC_CAM6M_MACADDR3_Pos (8)
3282
#define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos)
3284
#define EMAC_CAM6M_MACADDR4_Pos (16)
3285
#define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos)
3287
#define EMAC_CAM6M_MACADDR5_Pos (24)
3288
#define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos)
3290
#define EMAC_CAM6L_MACADDR0_Pos (16)
3291
#define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos)
3293
#define EMAC_CAM6L_MACADDR1_Pos (24)
3294
#define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos)
3296
#define EMAC_CAM7M_MACADDR2_Pos (0)
3297
#define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos)
3299
#define EMAC_CAM7M_MACADDR3_Pos (8)
3300
#define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos)
3302
#define EMAC_CAM7M_MACADDR4_Pos (16)
3303
#define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos)
3305
#define EMAC_CAM7M_MACADDR5_Pos (24)
3306
#define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos)
3308
#define EMAC_CAM7L_MACADDR0_Pos (16)
3309
#define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos)
3311
#define EMAC_CAM7L_MACADDR1_Pos (24)
3312
#define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos)
3314
#define EMAC_CAM8M_MACADDR2_Pos (0)
3315
#define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos)
3317
#define EMAC_CAM8M_MACADDR3_Pos (8)
3318
#define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos)
3320
#define EMAC_CAM8M_MACADDR4_Pos (16)
3321
#define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos)
3323
#define EMAC_CAM8M_MACADDR5_Pos (24)
3324
#define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos)
3326
#define EMAC_CAM8L_MACADDR0_Pos (16)
3327
#define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos)
3329
#define EMAC_CAM8L_MACADDR1_Pos (24)
3330
#define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos)
3332
#define EMAC_CAM9M_MACADDR2_Pos (0)
3333
#define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos)
3335
#define EMAC_CAM9M_MACADDR3_Pos (8)
3336
#define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos)
3338
#define EMAC_CAM9M_MACADDR4_Pos (16)
3339
#define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos)
3341
#define EMAC_CAM9M_MACADDR5_Pos (24)
3342
#define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos)
3344
#define EMAC_CAM9L_MACADDR0_Pos (16)
3345
#define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos)
3347
#define EMAC_CAM9L_MACADDR1_Pos (24)
3348
#define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos)
3350
#define EMAC_CAM10M_MACADDR2_Pos (0)
3351
#define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos)
3353
#define EMAC_CAM10M_MACADDR3_Pos (8)
3354
#define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos)
3356
#define EMAC_CAM10M_MACADDR4_Pos (16)
3357
#define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos)
3359
#define EMAC_CAM10M_MACADDR5_Pos (24)
3360
#define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos)
3362
#define EMAC_CAM10L_MACADDR0_Pos (16)
3363
#define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos)
3365
#define EMAC_CAM10L_MACADDR1_Pos (24)
3366
#define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos)
3368
#define EMAC_CAM11M_MACADDR2_Pos (0)
3369
#define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos)
3371
#define EMAC_CAM11M_MACADDR3_Pos (8)
3372
#define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos)
3374
#define EMAC_CAM11M_MACADDR4_Pos (16)
3375
#define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos)
3377
#define EMAC_CAM11M_MACADDR5_Pos (24)
3378
#define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos)
3380
#define EMAC_CAM11L_MACADDR0_Pos (16)
3381
#define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos)
3383
#define EMAC_CAM11L_MACADDR1_Pos (24)
3384
#define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos)
3386
#define EMAC_CAM12M_MACADDR2_Pos (0)
3387
#define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos)
3389
#define EMAC_CAM12M_MACADDR3_Pos (8)
3390
#define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos)
3392
#define EMAC_CAM12M_MACADDR4_Pos (16)
3393
#define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos)
3395
#define EMAC_CAM12M_MACADDR5_Pos (24)
3396
#define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos)
3398
#define EMAC_CAM12L_MACADDR0_Pos (16)
3399
#define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos)
3401
#define EMAC_CAM12L_MACADDR1_Pos (24)
3402
#define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos)
3404
#define EMAC_CAM13M_MACADDR2_Pos (0)
3405
#define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos)
3407
#define EMAC_CAM13M_MACADDR3_Pos (8)
3408
#define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos)
3410
#define EMAC_CAM13M_MACADDR4_Pos (16)
3411
#define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos)
3413
#define EMAC_CAM13M_MACADDR5_Pos (24)
3414
#define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos)
3416
#define EMAC_CAM13L_MACADDR0_Pos (16)
3417
#define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos)
3419
#define EMAC_CAM13L_MACADDR1_Pos (24)
3420
#define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos)
3422
#define EMAC_CAM14M_MACADDR2_Pos (0)
3423
#define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos)
3425
#define EMAC_CAM14M_MACADDR3_Pos (8)
3426
#define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos)
3428
#define EMAC_CAM14M_MACADDR4_Pos (16)
3429
#define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos)
3431
#define EMAC_CAM14M_MACADDR5_Pos (24)
3432
#define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos)
3434
#define EMAC_CAM14L_MACADDR0_Pos (16)
3435
#define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos)
3437
#define EMAC_CAM14L_MACADDR1_Pos (24)
3438
#define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos)
3440
#define EMAC_CAM15MSB_OPCODE_Pos (0)
3441
#define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos)
3443
#define EMAC_CAM15MSB_LENGTH_Pos (16)
3444
#define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos)
3446
#define EMAC_CAM15LSB_OPERAND_Pos (24)
3447
#define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos)
3449
#define EMAC_TXDSA_TXDSA_Pos (0)
3450
#define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos)
3452
#define EMAC_RXDSA_RXDSA_Pos (0)
3453
#define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos)
3455
#define EMAC_CTL_RXON_Pos (0)
3456
#define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos)
3458
#define EMAC_CTL_ALP_Pos (1)
3459
#define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos)
3461
#define EMAC_CTL_ARP_Pos (2)
3462
#define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos)
3464
#define EMAC_CTL_ACP_Pos (3)
3465
#define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos)
3467
#define EMAC_CTL_AEP_Pos (4)
3468
#define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos)
3470
#define EMAC_CTL_STRIPCRC_Pos (5)
3471
#define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos)
3473
#define EMAC_CTL_WOLEN_Pos (6)
3474
#define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos)
3476
#define EMAC_CTL_TXON_Pos (8)
3477
#define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos)
3479
#define EMAC_CTL_NODEF_Pos (9)
3480
#define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos)
3482
#define EMAC_CTL_SDPZ_Pos (16)
3483
#define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos)
3485
#define EMAC_CTL_SQECHKEN_Pos (17)
3486
#define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos)
3488
#define EMAC_CTL_FUDUP_Pos (18)
3489
#define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos)
3491
#define EMAC_CTL_RMIIRXCTL_Pos (19)
3492
#define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos)
3494
#define EMAC_CTL_OPMODE_Pos (20)
3495
#define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos)
3497
#define EMAC_CTL_RMIIEN_Pos (22)
3498
#define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos)
3500
#define EMAC_CTL_RST_Pos (24)
3501
#define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos)
3503
#define EMAC_MIIMDAT_DATA_Pos (0)
3504
#define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos)
3506
#define EMAC_MIIMCTL_PHYREG_Pos (0)
3507
#define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos)
3509
#define EMAC_MIIMCTL_PHYADDR_Pos (8)
3510
#define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos)
3512
#define EMAC_MIIMCTL_WRITE_Pos (16)
3513
#define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos)
3515
#define EMAC_MIIMCTL_BUSY_Pos (17)
3516
#define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos)
3518
#define EMAC_MIIMCTL_PREAMSP_Pos (18)
3519
#define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos)
3521
#define EMAC_MIIMCTL_MDCON_Pos (19)
3522
#define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos)
3524
#define EMAC_FIFOCTL_RXFIFOTH_Pos (0)
3525
#define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos)
3527
#define EMAC_FIFOCTL_TXFIFOTH_Pos (8)
3528
#define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos)
3530
#define EMAC_FIFOCTL_BURSTLEN_Pos (20)
3531
#define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos)
3533
#define EMAC_TXST_TXST_Pos (0)
3534
#define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos)
3536
#define EMAC_RXST_RXST_Pos (0)
3537
#define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos)
3539
#define EMAC_MRFL_MRFL_Pos (0)
3540
#define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos)
3542
#define EMAC_INTEN_RXIEN_Pos (0)
3543
#define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos)
3545
#define EMAC_INTEN_CRCEIEN_Pos (1)
3546
#define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos)
3548
#define EMAC_INTEN_RXOVIEN_Pos (2)
3549
#define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos)
3551
#define EMAC_INTEN_LPIEN_Pos (3)
3552
#define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos)
3554
#define EMAC_INTEN_RXGDIEN_Pos (4)
3555
#define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos)
3557
#define EMAC_INTEN_ALIEIEN_Pos (5)
3558
#define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos)
3560
#define EMAC_INTEN_RPIEN_Pos (6)
3561
#define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos)
3563
#define EMAC_INTEN_MPCOVIEN_Pos (7)
3564
#define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos)
3566
#define EMAC_INTEN_MFLEIEN_Pos (8)
3567
#define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos)
3569
#define EMAC_INTEN_DENIEN_Pos (9)
3570
#define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos)
3572
#define EMAC_INTEN_RDUIEN_Pos (10)
3573
#define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos)
3575
#define EMAC_INTEN_RXBEIEN_Pos (11)
3576
#define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos)
3578
#define EMAC_INTEN_CFRIEN_Pos (14)
3579
#define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos)
3581
#define EMAC_INTEN_WOLIEN_Pos (15)
3582
#define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos)
3584
#define EMAC_INTEN_TXIEN_Pos (16)
3585
#define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos)
3587
#define EMAC_INTEN_TXUDIEN_Pos (17)
3588
#define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos)
3590
#define EMAC_INTEN_TXCPIEN_Pos (18)
3591
#define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos)
3593
#define EMAC_INTEN_EXDEFIEN_Pos (19)
3594
#define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos)
3596
#define EMAC_INTEN_NCSIEN_Pos (20)
3597
#define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos)
3599
#define EMAC_INTEN_TXABTIEN_Pos (21)
3600
#define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos)
3602
#define EMAC_INTEN_LCIEN_Pos (22)
3603
#define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos)
3605
#define EMAC_INTEN_TDUIEN_Pos (23)
3606
#define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos)
3608
#define EMAC_INTEN_TXBEIEN_Pos (24)
3609
#define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos)
3611
#define EMAC_INTEN_TSALMIEN_Pos (28)
3612
#define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos)
3614
#define EMAC_INTSTS_RXIF_Pos (0)
3615
#define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos)
3617
#define EMAC_INTSTS_CRCEIF_Pos (1)
3618
#define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos)
3620
#define EMAC_INTSTS_RXOVIF_Pos (2)
3621
#define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos)
3623
#define EMAC_INTSTS_LPIF_Pos (3)
3624
#define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos)
3626
#define EMAC_INTSTS_RXGDIF_Pos (4)
3627
#define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos)
3629
#define EMAC_INTSTS_ALIEIF_Pos (5)
3630
#define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos)
3632
#define EMAC_INTSTS_RPIF_Pos (6)
3633
#define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos)
3635
#define EMAC_INTSTS_MPCOVIF_Pos (7)
3636
#define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos)
3638
#define EMAC_INTSTS_MFLEIF_Pos (8)
3639
#define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos)
3641
#define EMAC_INTSTS_DENIF_Pos (9)
3642
#define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos)
3644
#define EMAC_INTSTS_RDUIF_Pos (10)
3645
#define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos)
3647
#define EMAC_INTSTS_RXBEIF_Pos (11)
3648
#define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos)
3650
#define EMAC_INTSTS_CFRIF_Pos (14)
3651
#define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos)
3653
#define EMAC_INTSTS_WOLIF_Pos (15)
3654
#define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos)
3656
#define EMAC_INTSTS_TXIF_Pos (16)
3657
#define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos)
3659
#define EMAC_INTSTS_TXUDIF_Pos (17)
3660
#define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos)
3662
#define EMAC_INTSTS_TXCPIF_Pos (18)
3663
#define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos)
3665
#define EMAC_INTSTS_EXDEFIF_Pos (19)
3666
#define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos)
3668
#define EMAC_INTSTS_NCSIF_Pos (20)
3669
#define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos)
3671
#define EMAC_INTSTS_TXABTIF_Pos (21)
3672
#define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos)
3674
#define EMAC_INTSTS_LCIF_Pos (22)
3675
#define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos)
3677
#define EMAC_INTSTS_TDUIF_Pos (23)
3678
#define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos)
3680
#define EMAC_INTSTS_TXBEIF_Pos (24)
3681
#define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos)
3683
#define EMAC_INTSTS_TSALMIF_Pos (28)
3684
#define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos)
3686
#define EMAC_GENSTS_CFR_Pos (0)
3687
#define EMAC_GENSTS_CFR_Msk (0x1ul << EMAC_GENSTS_CFR_Pos)
3689
#define EMAC_GENSTS_RXHALT_Pos (1)
3690
#define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos)
3692
#define EMAC_GENSTS_RXFFULL_Pos (2)
3693
#define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos)
3695
#define EMAC_GENSTS_COLCNT_Pos (4)
3696
#define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos)
3698
#define EMAC_GENSTS_DEF_Pos (8)
3699
#define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos)
3701
#define EMAC_GENSTS_TXPAUSED_Pos (9)
3702
#define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos)
3704
#define EMAC_GENSTS_SQE_Pos (10)
3705
#define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos)
3707
#define EMAC_GENSTS_TXHALT_Pos (11)
3708
#define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos)
3710
#define EMAC_GENSTS_RPSTS_Pos (12)
3711
#define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos)
3713
#define EMAC_MPCNT_MPCNT_Pos (0)
3714
#define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos)
3716
#define EMAC_RPCNT_RPCNT_Pos (0)
3717
#define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos)
3719
#define EMAC_FRSTS_RXFLT_Pos (0)
3720
#define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos)
3722
#define EMAC_CTXDSA_CTXDSA_Pos (0)
3723
#define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos)
3725
#define EMAC_CTXBSA_CTXBSA_Pos (0)
3726
#define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos)
3728
#define EMAC_CRXDSA_CRXDSA_Pos (0)
3729
#define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos)
3731
#define EMAC_CRXBSA_CRXBSA_Pos (0)
3732
#define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos)
3734
#define EMAC_TSCTL_TSEN_Pos (0)
3735
#define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos)
3737
#define EMAC_TSCTL_TSIEN_Pos (1)
3738
#define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos)
3740
#define EMAC_TSCTL_TSMODE_Pos (2)
3741
#define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos)
3743
#define EMAC_TSCTL_TSUPDATE_Pos (3)
3744
#define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos)
3746
#define EMAC_TSCTL_TSALMEN_Pos (5)
3747
#define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos)
3749
#define EMAC_TSSEC_SEC_Pos (0)
3750
#define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos)
3752
#define EMAC_TSSUBSEC_SUBSEC_Pos (0)
3753
#define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos)
3755
#define EMAC_TSINC_CNTINC_Pos (0)
3756
#define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos)
3758
#define EMAC_TSADDEND_ADDEND_Pos (0)
3759
#define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos)
3761
#define EMAC_UPDSEC_SEC_Pos (0)
3762
#define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos)
3764
#define EMAC_UPDSUBSEC_SUBSEC_Pos (0)
3765
#define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos)
3767
#define EMAC_ALMSEC_SEC_Pos (0)
3768
#define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos)
3770
#define EMAC_ALMSUBSEC_SUBSEC_Pos (0)
3771
#define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos)
/* EMAC_CONST */
/* end of EMAC register group */
/* end of REGISTER group */
3776
3777
#if defined ( __CC_ARM )
3778
#pragma no_anon_unions
3779
#endif
3780
3781
#endif
/* __EMAC_REG_H__ */
EMAC_T
Definition:
emac_reg.h:27
EMAC_T::CAM11L
__IO uint32_t CAM11L
Definition:
emac_reg.h:3098
EMAC_T::CAM8M
__IO uint32_t CAM8M
Definition:
emac_reg.h:3091
EMAC_T::CAM4L
__IO uint32_t CAM4L
Definition:
emac_reg.h:3084
EMAC_T::CRXBSA
__I uint32_t CRXBSA
Definition:
emac_reg.h:3128
EMAC_T::CAM10M
__IO uint32_t CAM10M
Definition:
emac_reg.h:3095
EMAC_T::CTL
__IO uint32_t CTL
Definition:
emac_reg.h:3109
EMAC_T::CAM9L
__IO uint32_t CAM9L
Definition:
emac_reg.h:3094
EMAC_T::MRFL
__IO uint32_t MRFL
Definition:
emac_reg.h:3115
EMAC_T::CAM12L
__IO uint32_t CAM12L
Definition:
emac_reg.h:3100
EMAC_T::TXDSA
__IO uint32_t TXDSA
Definition:
emac_reg.h:3107
EMAC_T::TSSUBSEC
__I uint32_t TSSUBSEC
Definition:
emac_reg.h:3137
EMAC_T::RXST
__O uint32_t RXST
Definition:
emac_reg.h:3114
EMAC_T::CAM8L
__IO uint32_t CAM8L
Definition:
emac_reg.h:3092
EMAC_T::ALMSUBSEC
__IO uint32_t ALMSUBSEC
Definition:
emac_reg.h:3143
EMAC_T::CAM1M
__IO uint32_t CAM1M
Definition:
emac_reg.h:3077
EMAC_T::UPDSEC
__IO uint32_t UPDSEC
Definition:
emac_reg.h:3140
EMAC_T::CAM7M
__IO uint32_t CAM7M
Definition:
emac_reg.h:3089
EMAC_T::CAM2M
__IO uint32_t CAM2M
Definition:
emac_reg.h:3079
EMAC_T::CAM6M
__IO uint32_t CAM6M
Definition:
emac_reg.h:3087
EMAC_T::CAM0L
__IO uint32_t CAM0L
Definition:
emac_reg.h:3076
EMAC_T::CAM14L
__IO uint32_t CAM14L
Definition:
emac_reg.h:3104
EMAC_T::ALMSEC
__IO uint32_t ALMSEC
Definition:
emac_reg.h:3142
EMAC_T::CAM14M
__IO uint32_t CAM14M
Definition:
emac_reg.h:3103
EMAC_T::CAM5L
__IO uint32_t CAM5L
Definition:
emac_reg.h:3086
EMAC_T::CAMCTL
__IO uint32_t CAMCTL
Definition:
emac_reg.h:3073
EMAC_T::FIFOCTL
__IO uint32_t FIFOCTL
Definition:
emac_reg.h:3112
EMAC_T::CAM1L
__IO uint32_t CAM1L
Definition:
emac_reg.h:3078
EMAC_T::CAM7L
__IO uint32_t CAM7L
Definition:
emac_reg.h:3090
EMAC_T::RXDSA
__IO uint32_t RXDSA
Definition:
emac_reg.h:3108
EMAC_T::TSADDEND
__IO uint32_t TSADDEND
Definition:
emac_reg.h:3139
EMAC_T::CAM5M
__IO uint32_t CAM5M
Definition:
emac_reg.h:3085
EMAC_T::CAM12M
__IO uint32_t CAM12M
Definition:
emac_reg.h:3099
EMAC_T::CAM0M
__IO uint32_t CAM0M
Definition:
emac_reg.h:3075
EMAC_T::CAM13M
__IO uint32_t CAM13M
Definition:
emac_reg.h:3101
EMAC_T::CRXDSA
__I uint32_t CRXDSA
Definition:
emac_reg.h:3127
EMAC_T::CTXBSA
__I uint32_t CTXBSA
Definition:
emac_reg.h:3126
EMAC_T::UPDSUBSEC
__IO uint32_t UPDSUBSEC
Definition:
emac_reg.h:3141
EMAC_T::GENSTS
__IO uint32_t GENSTS
Definition:
emac_reg.h:3118
EMAC_T::CTXDSA
__I uint32_t CTXDSA
Definition:
emac_reg.h:3125
EMAC_T::CAM11M
__IO uint32_t CAM11M
Definition:
emac_reg.h:3097
EMAC_T::CAM15MSB
__IO uint32_t CAM15MSB
Definition:
emac_reg.h:3105
EMAC_T::MIIMCTL
__IO uint32_t MIIMCTL
Definition:
emac_reg.h:3111
EMAC_T::CAMEN
__IO uint32_t CAMEN
Definition:
emac_reg.h:3074
EMAC_T::CAM13L
__IO uint32_t CAM13L
Definition:
emac_reg.h:3102
EMAC_T::TSINC
__IO uint32_t TSINC
Definition:
emac_reg.h:3138
EMAC_T::TSSEC
__I uint32_t TSSEC
Definition:
emac_reg.h:3136
EMAC_T::FRSTS
__IO uint32_t FRSTS
Definition:
emac_reg.h:3124
EMAC_T::TSCTL
__IO uint32_t TSCTL
Definition:
emac_reg.h:3132
EMAC_T::RPCNT
__I uint32_t RPCNT
Definition:
emac_reg.h:3120
EMAC_T::CAM15LSB
__IO uint32_t CAM15LSB
Definition:
emac_reg.h:3106
EMAC_T::CAM6L
__IO uint32_t CAM6L
Definition:
emac_reg.h:3088
EMAC_T::CAM4M
__IO uint32_t CAM4M
Definition:
emac_reg.h:3083
EMAC_T::CAM3L
__IO uint32_t CAM3L
Definition:
emac_reg.h:3082
EMAC_T::TXST
__O uint32_t TXST
Definition:
emac_reg.h:3113
EMAC_T::CAM9M
__IO uint32_t CAM9M
Definition:
emac_reg.h:3093
EMAC_T::INTEN
__IO uint32_t INTEN
Definition:
emac_reg.h:3116
EMAC_T::CAM2L
__IO uint32_t CAM2L
Definition:
emac_reg.h:3080
EMAC_T::MPCNT
__IO uint32_t MPCNT
Definition:
emac_reg.h:3119
EMAC_T::MIIMDAT
__IO uint32_t MIIMDAT
Definition:
emac_reg.h:3110
EMAC_T::INTSTS
__IO uint32_t INTSTS
Definition:
emac_reg.h:3117
EMAC_T::CAM10L
__IO uint32_t CAM10L
Definition:
emac_reg.h:3096
EMAC_T::CAM3M
__IO uint32_t CAM3M
Definition:
emac_reg.h:3081
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