M480 BSP V3.05.006
The Board Support Package for M480 Series
Data Structures
timer_reg.h File Reference

TIMER register definition header file. More...

Go to the source code of this file.

Data Structures

struct  TIMER_T
 

Macros

#define TIMER_CTL_PSC_Pos   (0)
 
#define TIMER_CTL_PSC_Msk   (0xfful << TIMER_CTL_PSC_Pos)
 
#define TIMER_CTL_INTRGEN_Pos   (19)
 
#define TIMER_CTL_INTRGEN_Msk   (0x1ul << TIMER_CTL_INTRGEN_Pos)
 
#define TIMER_CTL_PERIOSEL_Pos   (20)
 
#define TIMER_CTL_PERIOSEL_Msk   (0x1ul << TIMER_CTL_PERIOSEL_Pos)
 
#define TIMER_CTL_TGLPINSEL_Pos   (21)
 
#define TIMER_CTL_TGLPINSEL_Msk   (0x1ul << TIMER_CTL_TGLPINSEL_Pos)
 
#define TIMER_CTL_CAPSRC_Pos   (22)
 
#define TIMER_CTL_CAPSRC_Msk   (0x1ul << TIMER_CTL_CAPSRC_Pos)
 
#define TIMER_CTL_WKEN_Pos   (23)
 
#define TIMER_CTL_WKEN_Msk   (0x1ul << TIMER_CTL_WKEN_Pos)
 
#define TIMER_CTL_EXTCNTEN_Pos   (24)
 
#define TIMER_CTL_EXTCNTEN_Msk   (0x1ul << TIMER_CTL_EXTCNTEN_Pos)
 
#define TIMER_CTL_ACTSTS_Pos   (25)
 
#define TIMER_CTL_ACTSTS_Msk   (0x1ul << TIMER_CTL_ACTSTS_Pos)
 
#define TIMER_CTL_OPMODE_Pos   (27)
 
#define TIMER_CTL_OPMODE_Msk   (0x3ul << TIMER_CTL_OPMODE_Pos)
 
#define TIMER_CTL_INTEN_Pos   (29)
 
#define TIMER_CTL_INTEN_Msk   (0x1ul << TIMER_CTL_INTEN_Pos)
 
#define TIMER_CTL_CNTEN_Pos   (30)
 
#define TIMER_CTL_CNTEN_Msk   (0x1ul << TIMER_CTL_CNTEN_Pos)
 
#define TIMER_CTL_ICEDEBUG_Pos   (31)
 
#define TIMER_CTL_ICEDEBUG_Msk   (0x1ul << TIMER_CTL_ICEDEBUG_Pos)
 
#define TIMER_CMP_CMPDAT_Pos   (0)
 
#define TIMER_CMP_CMPDAT_Msk   (0xfffffful << TIMER_CMP_CMPDAT_Pos)
 
#define TIMER_INTSTS_TIF_Pos   (0)
 
#define TIMER_INTSTS_TIF_Msk   (0x1ul << TIMER_INTSTS_TIF_Pos)
 
#define TIMER_INTSTS_TWKF_Pos   (1)
 
#define TIMER_INTSTS_TWKF_Msk   (0x1ul << TIMER_INTSTS_TWKF_Pos)
 
#define TIMER_CNT_CNT_Pos   (0)
 
#define TIMER_CNT_CNT_Msk   (0xfffffful << TIMER_CNT_CNT_Pos)
 
#define TIMER_CNT_RSTACT_Pos   (31)
 
#define TIMER_CNT_RSTACT_Msk   (0x1ul << TIMER_CNT_RSTACT_Pos)
 
#define TIMER_CAP_CAPDAT_Pos   (0)
 
#define TIMER_CAP_CAPDAT_Msk   (0xfffffful << TIMER_CAP_CAPDAT_Pos)
 
#define TIMER_EXTCTL_CNTPHASE_Pos   (0)
 
#define TIMER_EXTCTL_CNTPHASE_Msk   (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos)
 
#define TIMER_EXTCTL_CAPEN_Pos   (3)
 
#define TIMER_EXTCTL_CAPEN_Msk   (0x1ul << TIMER_EXTCTL_CAPEN_Pos)
 
#define TIMER_EXTCTL_CAPFUNCS_Pos   (4)
 
#define TIMER_EXTCTL_CAPFUNCS_Msk   (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos)
 
#define TIMER_EXTCTL_CAPIEN_Pos   (5)
 
#define TIMER_EXTCTL_CAPIEN_Msk   (0x1ul << TIMER_EXTCTL_CAPIEN_Pos)
 
#define TIMER_EXTCTL_CAPDBEN_Pos   (6)
 
#define TIMER_EXTCTL_CAPDBEN_Msk   (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos)
 
#define TIMER_EXTCTL_CNTDBEN_Pos   (7)
 
#define TIMER_EXTCTL_CNTDBEN_Msk   (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos)
 
#define TIMER_EXTCTL_ICAPSEL_Pos   (8)
 
#define TIMER_EXTCTL_ICAPSEL_Msk   (0x7ul << TIMER_EXTCTL_ICAPSEL_Pos)
 
#define TIMER_EXTCTL_CAPEDGE_Pos   (12)
 
#define TIMER_EXTCTL_CAPEDGE_Msk   (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos)
 
#define TIMER_EXTCTL_ECNTSSEL_Pos   (16)
 
#define TIMER_EXTCTL_ECNTSSEL_Msk   (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos)
 
#define TIMER_EXTCTL_CAPDIVSCL_Pos   (28)
 
#define TIMER_EXTCTL_CAPDIVSCL_Msk   (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos)
 
#define TIMER_EINTSTS_CAPIF_Pos   (0)
 
#define TIMER_EINTSTS_CAPIF_Msk   (0x1ul << TIMER_EINTSTS_CAPIF_Pos)
 
#define TIMER_TRGCTL_TRGSSEL_Pos   (0)
 
#define TIMER_TRGCTL_TRGSSEL_Msk   (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos)
 
#define TIMER_TRGCTL_TRGEPWM_Pos   (1)
 
#define TIMER_TRGCTL_TRGEPWM_Msk   (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos)
 
#define TIMER_TRGCTL_TRGEADC_Pos   (2)
 
#define TIMER_TRGCTL_TRGEADC_Msk   (0x1ul << TIMER_TRGCTL_TRGEADC_Pos)
 
#define TIMER_TRGCTL_TRGDAC_Pos   (3)
 
#define TIMER_TRGCTL_TRGDAC_Msk   (0x1ul << TIMER_TRGCTL_TRGDAC_Pos)
 
#define TIMER_TRGCTL_TRGPDMA_Pos   (4)
 
#define TIMER_TRGCTL_TRGPDMA_Msk   (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos)
 
#define TIMER_ALTCTL_FUNCSEL_Pos   (0)
 
#define TIMER_ALTCTL_FUNCSEL_Msk   (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos)
 
#define TIMER_PWMCTL_CNTEN_Pos   (0)
 
#define TIMER_PWMCTL_CNTEN_Msk   (0x1ul << TIMER_PWMCTL_CNTEN_Pos)
 
#define TIMER_PWMCTL_CNTTYPE_Pos   (1)
 
#define TIMER_PWMCTL_CNTTYPE_Msk   (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos)
 
#define TIMER_PWMCTL_CNTMODE_Pos   (3)
 
#define TIMER_PWMCTL_CNTMODE_Msk   (0x1ul << TIMER_PWMCTL_CNTMODE_Pos)
 
#define TIMER_PWMCTL_CTRLD_Pos   (8)
 
#define TIMER_PWMCTL_CTRLD_Msk   (0x1ul << TIMER_PWMCTL_CTRLD_Pos)
 
#define TIMER_PWMCTL_IMMLDEN_Pos   (9)
 
#define TIMER_PWMCTL_IMMLDEN_Msk   (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos)
 
#define TIMER_PWMCTL_OUTMODE_Pos   (16)
 
#define TIMER_PWMCTL_OUTMODE_Msk   (0x1ul << TIMER_PWMCTL_OUTMODE_Pos)
 
#define TIMER_PWMCTL_DBGHALT_Pos   (30)
 
#define TIMER_PWMCTL_DBGHALT_Msk   (0x1ul << TIMER_PWMCTL_DBGHALT_Pos)
 
#define TIMER_PWMCTL_DBGTRIOFF_Pos   (31)
 
#define TIMER_PWMCTL_DBGTRIOFF_Msk   (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos)
 
#define TIMER_PWMCLKSRC_CLKSRC_Pos   (0)
 
#define TIMER_PWMCLKSRC_CLKSRC_Msk   (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos)
 
#define TIMER_PWMCLKPSC_CLKPSC_Pos   (0)
 
#define TIMER_PWMCLKPSC_CLKPSC_Msk   (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos)
 
#define TIMER_PWMCNTCLR_CNTCLR_Pos   (0)
 
#define TIMER_PWMCNTCLR_CNTCLR_Msk   (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos)
 
#define TIMER_PWMPERIOD_PERIOD_Pos   (0)
 
#define TIMER_PWMPERIOD_PERIOD_Msk   (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos)
 
#define TIMER_PWMCMPDAT_CMP_Pos   (0)
 
#define TIMER_PWMCMPDAT_CMP_Msk   (0xfffful << TIMER_PWMCMPDAT_CMP_Pos)
 
#define TIMER_PWMDTCTL_DTCNT_Pos   (0)
 
#define TIMER_PWMDTCTL_DTCNT_Msk   (0xffful << TIMER_PWMDTCTL_DTCNT_Pos)
 
#define TIMER_PWMDTCTL_DTEN_Pos   (16)
 
#define TIMER_PWMDTCTL_DTEN_Msk   (0x1ul << TIMER_PWMDTCTL_DTEN_Pos)
 
#define TIMER_PWMDTCTL_DTCKSEL_Pos   (24)
 
#define TIMER_PWMDTCTL_DTCKSEL_Msk   (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos)
 
#define TIMER_PWMCNT_CNT_Pos   (0)
 
#define TIMER_PWMCNT_CNT_Msk   (0xfffful << TIMER_PWMCNT_CNT_Pos)
 
#define TIMER_PWMCNT_DIRF_Pos   (16)
 
#define TIMER_PWMCNT_DIRF_Msk   (0x1ul << TIMER_PWMCNT_DIRF_Pos)
 
#define TIMER_PWMMSKEN_MSKEN0_Pos   (0)
 
#define TIMER_PWMMSKEN_MSKEN0_Msk   (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos)
 
#define TIMER_PWMMSKEN_MSKEN1_Pos   (1)
 
#define TIMER_PWMMSKEN_MSKEN1_Msk   (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos)
 
#define TIMER_PWMMSK_MSKDAT0_Pos   (0)
 
#define TIMER_PWMMSK_MSKDAT0_Msk   (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos)
 
#define TIMER_PWMMSK_MSKDAT1_Pos   (1)
 
#define TIMER_PWMMSK_MSKDAT1_Msk   (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos)
 
#define TIMER_PWMBNF_BRKNFEN_Pos   (0)
 
#define TIMER_PWMBNF_BRKNFEN_Msk   (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos)
 
#define TIMER_PWMBNF_BRKNFSEL_Pos   (1)
 
#define TIMER_PWMBNF_BRKNFSEL_Msk   (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos)
 
#define TIMER_PWMBNF_BRKFCNT_Pos   (4)
 
#define TIMER_PWMBNF_BRKFCNT_Msk   (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos)
 
#define TIMER_PWMBNF_BRKPINV_Pos   (7)
 
#define TIMER_PWMBNF_BRKPINV_Msk   (0x1ul << TIMER_PWMBNF_BRKPINV_Pos)
 
#define TIMER_PWMBNF_BKPINSRC_Pos   (16)
 
#define TIMER_PWMBNF_BKPINSRC_Msk   (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos)
 
#define TIMER_PWMFAILBRK_CSSBRKEN_Pos   (0)
 
#define TIMER_PWMFAILBRK_CSSBRKEN_Msk   (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos)
 
#define TIMER_PWMFAILBRK_BODBRKEN_Pos   (1)
 
#define TIMER_PWMFAILBRK_BODBRKEN_Msk   (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos)
 
#define TIMER_PWMFAILBRK_RAMBRKEN_Pos   (2)
 
#define TIMER_PWMFAILBRK_RAMBRKEN_Msk   (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos)
 
#define TIMER_PWMFAILBRK_CORBRKEN_Pos   (3)
 
#define TIMER_PWMFAILBRK_CORBRKEN_Msk   (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos)
 
#define TIMER_PWMBRKCTL_CPO0EBEN_Pos   (0)
 
#define TIMER_PWMBRKCTL_CPO0EBEN_Msk   (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos)
 
#define TIMER_PWMBRKCTL_CPO1EBEN_Pos   (1)
 
#define TIMER_PWMBRKCTL_CPO1EBEN_Msk   (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos)
 
#define TIMER_PWMBRKCTL_BRKPEEN_Pos   (4)
 
#define TIMER_PWMBRKCTL_BRKPEEN_Msk   (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos)
 
#define TIMER_PWMBRKCTL_SYSEBEN_Pos   (7)
 
#define TIMER_PWMBRKCTL_SYSEBEN_Msk   (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos)
 
#define TIMER_PWMBRKCTL_CPO0LBEN_Pos   (8)
 
#define TIMER_PWMBRKCTL_CPO0LBEN_Msk   (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos)
 
#define TIMER_PWMBRKCTL_CPO1LBEN_Pos   (9)
 
#define TIMER_PWMBRKCTL_CPO1LBEN_Msk   (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos)
 
#define TIMER_PWMBRKCTL_BRKPLEN_Pos   (12)
 
#define TIMER_PWMBRKCTL_BRKPLEN_Msk   (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos)
 
#define TIMER_PWMBRKCTL_SYSLBEN_Pos   (15)
 
#define TIMER_PWMBRKCTL_SYSLBEN_Msk   (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos)
 
#define TIMER_PWMBRKCTL_BRKAEVEN_Pos   (16)
 
#define TIMER_PWMBRKCTL_BRKAEVEN_Msk   (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos)
 
#define TIMER_PWMBRKCTL_BRKAODD_Pos   (18)
 
#define TIMER_PWMBRKCTL_BRKAODD_Msk   (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos)
 
#define TIMER_PWMPOLCTL_PINV0_Pos   (0)
 
#define TIMER_PWMPOLCTL_PINV0_Msk   (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos)
 
#define TIMER_PWMPOLCTL_PINV1_Pos   (1)
 
#define TIMER_PWMPOLCTL_PINV1_Msk   (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos)
 
#define TIMER_PWMPOEN_POEN0_Pos   (0)
 
#define TIMER_PWMPOEN_POEN0_Msk   (0x1ul << TIMER_PWMPOEN_POEN0_Pos)
 
#define TIMER_PWMPOEN_POEN1_Pos   (1)
 
#define TIMER_PWMPOEN_POEN1_Msk   (0x1ul << TIMER_PWMPOEN_POEN1_Pos)
 
#define TIMER_PWMSWBRK_BRKETRG_Pos   (0)
 
#define TIMER_PWMSWBRK_BRKETRG_Msk   (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos)
 
#define TIMER_PWMSWBRK_BRKLTRG_Pos   (8)
 
#define TIMER_PWMSWBRK_BRKLTRG_Msk   (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos)
 
#define TIMER_PWMINTEN0_ZIEN_Pos   (0)
 
#define TIMER_PWMINTEN0_ZIEN_Msk   (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos)
 
#define TIMER_PWMINTEN0_PIEN_Pos   (1)
 
#define TIMER_PWMINTEN0_PIEN_Msk   (0x1ul << TIMER_PWMINTEN0_PIEN_Pos)
 
#define TIMER_PWMINTEN0_CMPUIEN_Pos   (2)
 
#define TIMER_PWMINTEN0_CMPUIEN_Msk   (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos)
 
#define TIMER_PWMINTEN0_CMPDIEN_Pos   (3)
 
#define TIMER_PWMINTEN0_CMPDIEN_Msk   (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos)
 
#define TIMER_PWMINTEN1_BRKEIEN_Pos   (0)
 
#define TIMER_PWMINTEN1_BRKEIEN_Msk   (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos)
 
#define TIMER_PWMINTEN1_BRKLIEN_Pos   (8)
 
#define TIMER_PWMINTEN1_BRKLIEN_Msk   (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos)
 
#define TIMER_PWMINTSTS0_ZIF_Pos   (0)
 
#define TIMER_PWMINTSTS0_ZIF_Msk   (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos)
 
#define TIMER_PWMINTSTS0_PIF_Pos   (1)
 
#define TIMER_PWMINTSTS0_PIF_Msk   (0x1ul << TIMER_PWMINTSTS0_PIF_Pos)
 
#define TIMER_PWMINTSTS0_CMPUIF_Pos   (2)
 
#define TIMER_PWMINTSTS0_CMPUIF_Msk   (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos)
 
#define TIMER_PWMINTSTS0_CMPDIF_Pos   (3)
 
#define TIMER_PWMINTSTS0_CMPDIF_Msk   (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos)
 
#define TIMER_PWMINTSTS1_BRKEIF0_Pos   (0)
 
#define TIMER_PWMINTSTS1_BRKEIF0_Msk   (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos)
 
#define TIMER_PWMINTSTS1_BRKEIF1_Pos   (1)
 
#define TIMER_PWMINTSTS1_BRKEIF1_Msk   (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos)
 
#define TIMER_PWMINTSTS1_BRKLIF0_Pos   (8)
 
#define TIMER_PWMINTSTS1_BRKLIF0_Msk   (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos)
 
#define TIMER_PWMINTSTS1_BRKLIF1_Pos   (9)
 
#define TIMER_PWMINTSTS1_BRKLIF1_Msk   (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos)
 
#define TIMER_PWMINTSTS1_BRKESTS0_Pos   (16)
 
#define TIMER_PWMINTSTS1_BRKESTS0_Msk   (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos)
 
#define TIMER_PWMINTSTS1_BRKESTS1_Pos   (17)
 
#define TIMER_PWMINTSTS1_BRKESTS1_Msk   (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos)
 
#define TIMER_PWMINTSTS1_BRKLSTS0_Pos   (24)
 
#define TIMER_PWMINTSTS1_BRKLSTS0_Msk   (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos)
 
#define TIMER_PWMINTSTS1_BRKLSTS1_Pos   (25)
 
#define TIMER_PWMINTSTS1_BRKLSTS1_Msk   (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos)
 
#define TIMER_PWMEADCTS_TRGSEL_Pos   (0)
 
#define TIMER_PWMEADCTS_TRGSEL_Msk   (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos)
 
#define TIMER_PWMEADCTS_TRGEN_Pos   (7)
 
#define TIMER_PWMEADCTS_TRGEN_Msk   (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos)
 
#define TIMER_PWMSCTL_SYNCMODE_Pos   (0)
 
#define TIMER_PWMSCTL_SYNCMODE_Msk   (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos)
 
#define TIMER_PWMSCTL_SYNCSRC_Pos   (8)
 
#define TIMER_PWMSCTL_SYNCSRC_Msk   (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos)
 
#define TIMER_PWMSTRG_STRGEN_Pos   (0)
 
#define TIMER_PWMSTRG_STRGEN_Msk   (0x1ul << TIMER_PWMSTRG_STRGEN_Pos)
 
#define TIMER_PWMSTATUS_CNTMAXF_Pos   (0)
 
#define TIMER_PWMSTATUS_CNTMAXF_Msk   (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos)
 
#define TIMER_PWMSTATUS_EADCTRGF_Pos   (16)
 
#define TIMER_PWMSTATUS_EADCTRGF_Msk   (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos)
 
#define TIMER_PWMPBUF_PBUF_Pos   (0)
 
#define TIMER_PWMPBUF_PBUF_Msk   (0xfffful << TIMER_PWMPBUF_PBUF_Pos)
 
#define TIMER_PWMCMPBUF_CMPBUF_Pos   (0)
 
#define TIMER_PWMCMPBUF_CMPBUF_Msk   (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos)
 

Detailed Description

TIMER register definition header file.

Version
V1.00

SPDX-License-Identifier: Apache-2.0

Definition in file timer_reg.h.