M480 BSP V3.05.006
The Board Support Package for M480 Series
i2c_reg.h
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1/**************************************************************************/
9#ifndef __I2C_REG_H__
10#define __I2C_REG_H__
11
12#if defined ( __CC_ARM )
13#pragma anon_unions
14#endif
15
26typedef struct
27{
28
29
1046 __IO uint32_t CTL0;
1047 __IO uint32_t ADDR0;
1048 __IO uint32_t DAT;
1049 __I uint32_t STATUS0;
1050 __IO uint32_t CLKDIV;
1051 __IO uint32_t TOCTL;
1052 __IO uint32_t ADDR1;
1053 __IO uint32_t ADDR2;
1054 __IO uint32_t ADDR3;
1055 __IO uint32_t ADDRMSK0;
1056 __IO uint32_t ADDRMSK1;
1057 __IO uint32_t ADDRMSK2;
1058 __IO uint32_t ADDRMSK3;
1060 __I uint32_t RESERVE0[2];
1062 __IO uint32_t WKCTL;
1063 __IO uint32_t WKSTS;
1064 __IO uint32_t CTL1;
1065 __IO uint32_t STATUS1;
1066 __IO uint32_t TMCTL;
1067 __IO uint32_t BUSCTL;
1068 __IO uint32_t BUSTCTL;
1069 __IO uint32_t BUSSTS;
1070 __IO uint32_t PKTSIZE;
1071 __I uint32_t PKTCRC;
1072 __IO uint32_t BUSTOUT;
1073 __IO uint32_t CLKTOUT;
1075} I2C_T;
1076
1082#define I2C_CTL0_AA_Pos (2)
1083#define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos)
1085#define I2C_CTL0_SI_Pos (3)
1086#define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos)
1088#define I2C_CTL0_STO_Pos (4)
1089#define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos)
1091#define I2C_CTL0_STA_Pos (5)
1092#define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos)
1094#define I2C_CTL0_I2CEN_Pos (6)
1095#define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos)
1097#define I2C_CTL0_INTEN_Pos (7)
1098#define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos)
1100#define I2C_ADDR0_GC_Pos (0)
1101#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos)
1103#define I2C_ADDR0_ADDR_Pos (1)
1104#define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos)
1106#define I2C_DAT_DAT_Pos (0)
1107#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos)
1109#define I2C_STATUS0_STATUS_Pos (0)
1110#define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos)
1112#define I2C_CLKDIV_DIVIDER_Pos (0)
1113#define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos)
1115#define I2C_TOCTL_TOIF_Pos (0)
1116#define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos)
1118#define I2C_TOCTL_TOCDIV4_Pos (1)
1119#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos)
1121#define I2C_TOCTL_TOCEN_Pos (2)
1122#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos)
1124#define I2C_ADDR1_GC_Pos (0)
1125#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos)
1127#define I2C_ADDR1_ADDR_Pos (1)
1128#define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos)
1130#define I2C_ADDR2_GC_Pos (0)
1131#define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos)
1133#define I2C_ADDR2_ADDR_Pos (1)
1134#define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos)
1136#define I2C_ADDR3_GC_Pos (0)
1137#define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos)
1139#define I2C_ADDR3_ADDR_Pos (1)
1140#define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos)
1142#define I2C_ADDRMSK0_ADDRMSK_Pos (1)
1143#define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos)
1145#define I2C_ADDRMSK1_ADDRMSK_Pos (1)
1146#define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos)
1148#define I2C_ADDRMSK2_ADDRMSK_Pos (1)
1149#define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos)
1151#define I2C_ADDRMSK3_ADDRMSK_Pos (1)
1152#define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos)
1154#define I2C_WKCTL_WKEN_Pos (0)
1155#define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos)
1157#define I2C_WKCTL_NHDBUSEN_Pos (7)
1158#define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos)
1160#define I2C_WKSTS_WKIF_Pos (0)
1161#define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos)
1163#define I2C_WKSTS_WKAKDONE_Pos (1)
1164#define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos)
1166#define I2C_WKSTS_WRSTSWK_Pos (2)
1167#define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos)
1169#define I2C_CTL1_TXPDMAEN_Pos (0)
1170#define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos)
1172#define I2C_CTL1_RXPDMAEN_Pos (1)
1173#define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos)
1175#define I2C_CTL1_PDMARST_Pos (2)
1176#define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos)
1178#define I2C_CTL1_PDMASTR_Pos (8)
1179#define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos)
1181#define I2C_CTL1_ADDR10EN_Pos (9)
1182#define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos)
1184#define I2C_STATUS1_ADMAT0_Pos (0)
1185#define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos)
1187#define I2C_STATUS1_ADMAT1_Pos (1)
1188#define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos)
1190#define I2C_STATUS1_ADMAT2_Pos (2)
1191#define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos)
1193#define I2C_STATUS1_ADMAT3_Pos (3)
1194#define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos)
1196#define I2C_STATUS1_ONBUSY_Pos (8)
1197#define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos)
1199#define I2C_TMCTL_STCTL_Pos (0)
1200#define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos)
1202#define I2C_TMCTL_HTCTL_Pos (16)
1203#define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos)
1205#define I2C_BUSCTL_ACKMEN_Pos (0)
1206#define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos)
1208#define I2C_BUSCTL_PECEN_Pos (1)
1209#define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos)
1211#define I2C_BUSCTL_BMDEN_Pos (2)
1212#define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos)
1214#define I2C_BUSCTL_BMHEN_Pos (3)
1215#define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos)
1217#define I2C_BUSCTL_ALERTEN_Pos (4)
1218#define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos)
1220#define I2C_BUSCTL_SCTLOSTS_Pos (5)
1221#define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos)
1223#define I2C_BUSCTL_SCTLOEN_Pos (6)
1224#define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos)
1226#define I2C_BUSCTL_BUSEN_Pos (7)
1227#define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos)
1229#define I2C_BUSCTL_PECTXEN_Pos (8)
1230#define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos)
1232#define I2C_BUSCTL_TIDLE_Pos (9)
1233#define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos)
1235#define I2C_BUSCTL_PECCLR_Pos (10)
1236#define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos)
1238#define I2C_BUSCTL_ACKM9SI_Pos (11)
1239#define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos)
1241#define I2C_BUSCTL_BCDIEN_Pos (12)
1242#define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos)
1244#define I2C_BUSCTL_PECDIEN_Pos (13)
1245#define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos)
1247#define I2C_BUSTCTL_BUSTOEN_Pos (0)
1248#define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos)
1250#define I2C_BUSTCTL_CLKTOEN_Pos (1)
1251#define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos)
1253#define I2C_BUSTCTL_BUSTOIEN_Pos (2)
1254#define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos)
1256#define I2C_BUSTCTL_CLKTOIEN_Pos (3)
1257#define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos)
1259#define I2C_BUSTCTL_TORSTEN_Pos (4)
1260#define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos)
1262#define I2C_BUSSTS_BUSY_Pos (0)
1263#define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos)
1265#define I2C_BUSSTS_BCDONE_Pos (1)
1266#define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos)
1268#define I2C_BUSSTS_PECERR_Pos (2)
1269#define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos)
1271#define I2C_BUSSTS_ALERT_Pos (3)
1272#define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos)
1274#define I2C_BUSSTS_SCTLDIN_Pos (4)
1275#define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos)
1277#define I2C_BUSSTS_BUSTO_Pos (5)
1278#define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos)
1280#define I2C_BUSSTS_CLKTO_Pos (6)
1281#define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos)
1283#define I2C_BUSSTS_PECDONE_Pos (7)
1284#define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos)
1286#define I2C_PKTSIZE_PLDSIZE_Pos (0)
1287#define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos)
1289#define I2C_PKTCRC_PECCRC_Pos (0)
1290#define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos)
1292#define I2C_BUSTOUT_BUSTO_Pos (0)
1293#define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos)
1295#define I2C_CLKTOUT_CLKTO_Pos (0)
1296#define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) /* I2C_CONST */ /* end of I2C register group */ /* end of REGISTER group */
1301
1302#if defined ( __CC_ARM )
1303#pragma no_anon_unions
1304#endif
1305
1306#endif /* __I2C_REG_H__ */
Definition: i2c_reg.h:27
__IO uint32_t CLKTOUT
Definition: i2c_reg.h:1073
__IO uint32_t ADDR2
Definition: i2c_reg.h:1053
__IO uint32_t BUSTCTL
Definition: i2c_reg.h:1068
__IO uint32_t ADDR3
Definition: i2c_reg.h:1054
__IO uint32_t ADDRMSK1
Definition: i2c_reg.h:1056
__IO uint32_t ADDR0
Definition: i2c_reg.h:1047
__IO uint32_t TOCTL
Definition: i2c_reg.h:1051
__IO uint32_t CLKDIV
Definition: i2c_reg.h:1050
__IO uint32_t DAT
Definition: i2c_reg.h:1048
__I uint32_t PKTCRC
Definition: i2c_reg.h:1071
__IO uint32_t ADDR1
Definition: i2c_reg.h:1052
__IO uint32_t BUSTOUT
Definition: i2c_reg.h:1072
__IO uint32_t STATUS1
Definition: i2c_reg.h:1065
__IO uint32_t CTL0
Definition: i2c_reg.h:1046
__IO uint32_t ADDRMSK2
Definition: i2c_reg.h:1057
__IO uint32_t BUSSTS
Definition: i2c_reg.h:1069
__IO uint32_t TMCTL
Definition: i2c_reg.h:1066
__IO uint32_t ADDRMSK0
Definition: i2c_reg.h:1055
__IO uint32_t BUSCTL
Definition: i2c_reg.h:1067
__IO uint32_t ADDRMSK3
Definition: i2c_reg.h:1058
__IO uint32_t CTL1
Definition: i2c_reg.h:1064
__IO uint32_t PKTSIZE
Definition: i2c_reg.h:1070
__I uint32_t STATUS0
Definition: i2c_reg.h:1049
__IO uint32_t WKSTS
Definition: i2c_reg.h:1063
__IO uint32_t WKCTL
Definition: i2c_reg.h:1062