M480 BSP V3.05.006
The Board Support Package for M480 Series
sc_reg.h
Go to the documentation of this file.
1/**************************************************************************/
9#ifndef __SC_REG_H__
10#define __SC_REG_H__
11
12#if defined ( __CC_ARM )
13#pragma anon_unions
14#endif
15
26typedef struct
27{
28
29
1484 __IO uint32_t DAT;
1485 __IO uint32_t CTL;
1486 __IO uint32_t ALTCTL;
1487 __IO uint32_t EGT;
1488 __IO uint32_t RXTOUT;
1489 __IO uint32_t ETUCTL;
1490 __IO uint32_t INTEN;
1491 __IO uint32_t INTSTS;
1492 __IO uint32_t STATUS;
1493 __IO uint32_t PINCTL;
1494 __IO uint32_t TMRCTL0;
1495 __IO uint32_t TMRCTL1;
1496 __IO uint32_t TMRCTL2;
1497 __IO uint32_t UARTCTL;
1499 __I uint32_t RESERVE0[5];
1501 __IO uint32_t ACTCTL;
1503} SC_T;
1504
1510#define SC_DAT_DAT_Pos (0)
1511#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos)
1513#define SC_CTL_SCEN_Pos (0)
1514#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos)
1516#define SC_CTL_RXOFF_Pos (1)
1517#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos)
1519#define SC_CTL_TXOFF_Pos (2)
1520#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos)
1522#define SC_CTL_AUTOCEN_Pos (3)
1523#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos)
1525#define SC_CTL_CONSEL_Pos (4)
1526#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos)
1528#define SC_CTL_RXTRGLV_Pos (6)
1529#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos)
1531#define SC_CTL_BGT_Pos (8)
1532#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos)
1534#define SC_CTL_TMRSEL_Pos (13)
1535#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos)
1537#define SC_CTL_NSB_Pos (15)
1538#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos)
1540#define SC_CTL_RXRTY_Pos (16)
1541#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos)
1543#define SC_CTL_RXRTYEN_Pos (19)
1544#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos)
1546#define SC_CTL_TXRTY_Pos (20)
1547#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos)
1549#define SC_CTL_TXRTYEN_Pos (23)
1550#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos)
1552#define SC_CTL_CDDBSEL_Pos (24)
1553#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos)
1555#define SC_CTL_CDLV_Pos (26)
1556#define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos)
1558#define SC_CTL_SYNC_Pos (30)
1559#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos)
1561#define SC_ALTCTL_TXRST_Pos (0)
1562#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos)
1564#define SC_ALTCTL_RXRST_Pos (1)
1565#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos)
1567#define SC_ALTCTL_DACTEN_Pos (2)
1568#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos)
1570#define SC_ALTCTL_ACTEN_Pos (3)
1571#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos)
1573#define SC_ALTCTL_WARSTEN_Pos (4)
1574#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos)
1576#define SC_ALTCTL_CNTEN0_Pos (5)
1577#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos)
1579#define SC_ALTCTL_CNTEN1_Pos (6)
1580#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos)
1582#define SC_ALTCTL_CNTEN2_Pos (7)
1583#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos)
1585#define SC_ALTCTL_INITSEL_Pos (8)
1586#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos)
1588#define SC_ALTCTL_ADACEN_Pos (11)
1589#define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos)
1591#define SC_ALTCTL_RXBGTEN_Pos (12)
1592#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos)
1594#define SC_ALTCTL_ACTSTS0_Pos (13)
1595#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos)
1597#define SC_ALTCTL_ACTSTS1_Pos (14)
1598#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos)
1600#define SC_ALTCTL_ACTSTS2_Pos (15)
1601#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos)
1603#define SC_ALTCTL_SYNC_Pos (31)
1604#define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos)
1606#define SC_EGT_EGT_Pos (0)
1607#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos)
1609#define SC_RXTOUT_RFTM_Pos (0)
1610#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos)
1612#define SC_ETUCTL_ETURDIV_Pos (0)
1613#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos)
1615#define SC_INTEN_RDAIEN_Pos (0)
1616#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos)
1618#define SC_INTEN_TBEIEN_Pos (1)
1619#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos)
1621#define SC_INTEN_TERRIEN_Pos (2)
1622#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos)
1624#define SC_INTEN_TMR0IEN_Pos (3)
1625#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos)
1627#define SC_INTEN_TMR1IEN_Pos (4)
1628#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos)
1630#define SC_INTEN_TMR2IEN_Pos (5)
1631#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos)
1633#define SC_INTEN_BGTIEN_Pos (6)
1634#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos)
1636#define SC_INTEN_CDIEN_Pos (7)
1637#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos)
1639#define SC_INTEN_INITIEN_Pos (8)
1640#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos)
1642#define SC_INTEN_RXTOIEN_Pos (9)
1643#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos)
1645#define SC_INTEN_ACERRIEN_Pos (10)
1646#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos)
1648#define SC_INTSTS_RDAIF_Pos (0)
1649#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos)
1651#define SC_INTSTS_TBEIF_Pos (1)
1652#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos)
1654#define SC_INTSTS_TERRIF_Pos (2)
1655#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos)
1657#define SC_INTSTS_TMR0IF_Pos (3)
1658#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos)
1660#define SC_INTSTS_TMR1IF_Pos (4)
1661#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos)
1663#define SC_INTSTS_TMR2IF_Pos (5)
1664#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos)
1666#define SC_INTSTS_BGTIF_Pos (6)
1667#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos)
1669#define SC_INTSTS_CDIF_Pos (7)
1670#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos)
1672#define SC_INTSTS_INITIF_Pos (8)
1673#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos)
1675#define SC_INTSTS_RXTOIF_Pos (9)
1676#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos)
1678#define SC_INTSTS_ACERRIF_Pos (10)
1679#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos)
1681#define SC_STATUS_RXOV_Pos (0)
1682#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos)
1684#define SC_STATUS_RXEMPTY_Pos (1)
1685#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos)
1687#define SC_STATUS_RXFULL_Pos (2)
1688#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos)
1690#define SC_STATUS_PEF_Pos (4)
1691#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos)
1693#define SC_STATUS_FEF_Pos (5)
1694#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos)
1696#define SC_STATUS_BEF_Pos (6)
1697#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos)
1699#define SC_STATUS_TXOV_Pos (8)
1700#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos)
1702#define SC_STATUS_TXEMPTY_Pos (9)
1703#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos)
1705#define SC_STATUS_TXFULL_Pos (10)
1706#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos)
1708#define SC_STATUS_CREMOVE_Pos (11)
1709#define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos)
1711#define SC_STATUS_CINSERT_Pos (12)
1712#define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos)
1714#define SC_STATUS_CDPINSTS_Pos (13)
1715#define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos)
1717#define SC_STATUS_RXPOINT_Pos (16)
1718#define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos)
1720#define SC_STATUS_RXRERR_Pos (21)
1721#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos)
1723#define SC_STATUS_RXOVERR_Pos (22)
1724#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos)
1726#define SC_STATUS_RXACT_Pos (23)
1727#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos)
1729#define SC_STATUS_TXPOINT_Pos (24)
1730#define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos)
1732#define SC_STATUS_TXRERR_Pos (29)
1733#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos)
1735#define SC_STATUS_TXOVERR_Pos (30)
1736#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos)
1738#define SC_STATUS_TXACT_Pos (31)
1739#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos)
1741#define SC_PINCTL_PWREN_Pos (0)
1742#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos)
1744#define SC_PINCTL_RSTEN_Pos (1)
1745#define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos)
1747#define SC_PINCTL_CLKKEEP_Pos (6)
1748#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos)
1750#define SC_PINCTL_SCDATA_Pos (9)
1751#define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos)
1753#define SC_PINCTL_PWRINV_Pos (11)
1754#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos)
1756#define SC_PINCTL_DATASTS_Pos (16)
1757#define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos)
1759#define SC_PINCTL_PWRSTS_Pos (17)
1760#define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos)
1762#define SC_PINCTL_RSTSTS_Pos (18)
1763#define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos)
1765#define SC_PINCTL_SYNC_Pos (30)
1766#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos)
1768#define SC_TMRCTL0_CNT_Pos (0)
1769#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos)
1771#define SC_TMRCTL0_OPMODE_Pos (24)
1772#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos)
1774#define SC_TMRCTL0_SYNC_Pos (31)
1775#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos)
1777#define SC_TMRCTL1_CNT_Pos (0)
1778#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos)
1780#define SC_TMRCTL1_OPMODE_Pos (24)
1781#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos)
1783#define SC_TMRCTL1_SYNC_Pos (31)
1784#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos)
1786#define SC_TMRCTL2_CNT_Pos (0)
1787#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos)
1789#define SC_TMRCTL2_OPMODE_Pos (24)
1790#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos)
1792#define SC_TMRCTL2_SYNC_Pos (31)
1793#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos)
1795#define SC_UARTCTL_UARTEN_Pos (0)
1796#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos)
1798#define SC_UARTCTL_WLS_Pos (4)
1799#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos)
1801#define SC_UARTCTL_PBOFF_Pos (6)
1802#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos)
1804#define SC_UARTCTL_OPE_Pos (7)
1805#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos)
1807#define SC_ACTCTL_T1EXT_Pos (0)
1808#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /* SC_CONST */ /* end of SC register group */ /* end of REGISTER group */
1813
1814#if defined ( __CC_ARM )
1815#pragma no_anon_unions
1816#endif
1817
1818#endif /* __SC_REG_H__ */
Definition: sc_reg.h:27
__IO uint32_t DAT
Definition: sc_reg.h:1484
__IO uint32_t TMRCTL2
Definition: sc_reg.h:1496
__IO uint32_t ALTCTL
Definition: sc_reg.h:1486
__IO uint32_t ETUCTL
Definition: sc_reg.h:1489
__IO uint32_t INTEN
Definition: sc_reg.h:1490
__IO uint32_t ACTCTL
Definition: sc_reg.h:1501
__IO uint32_t CTL
Definition: sc_reg.h:1485
__IO uint32_t STATUS
Definition: sc_reg.h:1492
__IO uint32_t PINCTL
Definition: sc_reg.h:1493
__IO uint32_t TMRCTL0
Definition: sc_reg.h:1494
__IO uint32_t TMRCTL1
Definition: sc_reg.h:1495
__IO uint32_t INTSTS
Definition: sc_reg.h:1491
__IO uint32_t UARTCTL
Definition: sc_reg.h:1497
__IO uint32_t RXTOUT
Definition: sc_reg.h:1488
__IO uint32_t EGT
Definition: sc_reg.h:1487