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Mini51 BSP
V3.02.002
The Board Support Package for Mini51 Series
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Macros | |
#define | SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->CNTRL2 |= SPI_CNTRL2_SLV_ABORT_Msk ) |
Abort the current transfer in slave 3-wire mode. More... | |
#define | SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk ) |
Clear the slave 3-wire mode start interrupt flag. More... | |
#define | SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_IF_Msk ) |
Clear the unit transfer interrupt flag. More... | |
#define | SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->CNTRL2 &= ~SPI_CNTRL2_NOSLVSEL_Msk ) |
Disable slave 3-wire mode. More... | |
#define | SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->CNTRL2 |= SPI_CNTRL2_NOSLVSEL_Msk ) |
Enable slave 3-wire mode. More... | |
#define | SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RX_FIFO_COUNT_Msk) >> SPI_STATUS_RX_FIFO_COUNT_Pos) & 0xf ) |
Get the count of available data in RX FIFO. More... | |
#define | SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk) == SPI_STATUS_RX_EMPTY_Msk ? 1:0 ) |
Get the Rx FIFO empty flag. More... | |
#define | SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk) == SPI_STATUS_TX_EMPTY_Msk ? 1:0 ) |
Get the Tx FIFO empty flag. More... | |
#define | SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TX_FULL_Msk) == SPI_STATUS_TX_FULL_Msk ? 1:0 ) |
Get the Tx FIFO full flag. More... | |
#define | SPI_READ_RX(spi) ( (spi)->RX ) |
Get the datum read from Rx FIFO. More... | |
#define | SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = u32TxData ) |
Write datum to TX register. More... | |
#define | SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CNTRL |= SPI_CNTRL_REORDER_Msk ) |
Enable byte reorder function. More... | |
#define | SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CNTRL &= ~SPI_CNTRL_REORDER_Msk ) |
Disable byte reorder function. More... | |
#define | SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_SP_CYCLE_Msk) | (u32SuspCycle << SPI_CNTRL_SP_CYCLE_Pos) ) |
Set the length of suspend interval. More... | |
#define | SPI_SET_LSB_FIRST(spi) ( (spi)->CNTRL |= SPI_CNTRL_LSB_Msk ) |
Set the SPI transfer sequence with LSB first. More... | |
#define | SPI_SET_MSB_FIRST(spi) ( (spi)->CNTRL &= ~SPI_CNTRL_LSB_Msk ) |
Set the SPI transfer sequence with MSB first. More... | |
#define | SPI_IS_BUSY(spi) ( ((spi)->CNTRL & SPI_CNTRL_GO_BUSY_Msk) == SPI_CNTRL_GO_BUSY_Msk ? 1:0 ) |
Get the SPI busy state. More... | |
#define | SPI_TRIGGER(spi) ( (spi)->CNTRL |= SPI_CNTRL_GO_BUSY_Msk ) |
Set the GO_BUSY bit to trigger SPI transfer. More... | |
Functions | |
static __INLINE void | SPI_SET_SS_HIGH (SPI_T *spi) |
Disable automatic slave select function and set SPI_SS pin to high state. More... | |
static __INLINE void | SPI_SET_SS_LOW (SPI_T *spi) |
Disable automatic slave select function and set SPI_SS pin to low state. More... | |
static __INLINE void | SPI_SET_DATA_WIDTH (SPI_T *spi, uint32_t u32Width) |
Set the data width of a SPI transaction. More... | |
uint32_t | SPI_Open (SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) |
This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB first and the automatic slave select function is disabled. In Slave mode, the u32BusClock must be NULL and the SPI clock divider setting will be 0. More... | |
void | SPI_Close (SPI_T *spi) |
Reset SPI module and disable SPI peripheral clock. More... | |
void | SPI_ClearRxFIFO (SPI_T *spi) |
Clear Rx FIFO buffer. More... | |
void | SPI_ClearTxFIFO (SPI_T *spi) |
Clear Tx FIFO buffer. More... | |
void | SPI_DisableAutoSS (SPI_T *spi) |
Disable the automatic slave select function. More... | |
void | SPI_EnableAutoSS (SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) |
Enable the automatic slave select function. Only available in Master mode. More... | |
uint32_t | SPI_SetBusClock (SPI_T *spi, uint32_t u32BusClock) |
Set the SPI bus clock. Only available in Master mode. More... | |
void | SPI_EnableFIFO (SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) |
Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations. More... | |
void | SPI_DisableFIFO (SPI_T *spi) |
Disable FIFO mode. More... | |
uint32_t | SPI_GetBusClock (SPI_T *spi) |
Get the actual frequency of SPI bus clock. Only available in Master mode. More... | |
void | SPI_EnableInt (SPI_T *spi, uint32_t u32Mask) |
Enable FIFO related interrupts specified by u32Mask parameter. More... | |
void | SPI_DisableInt (SPI_T *spi, uint32_t u32Mask) |
Disable FIFO related interrupts specified by u32Mask parameter. More... | |
#define SPI_ABORT_3WIRE_TRANSFER | ( | spi | ) | ( (spi)->CNTRL2 |= SPI_CNTRL2_SLV_ABORT_Msk ) |
#define SPI_CLR_3WIRE_START_INT_FLAG | ( | spi | ) | ( (spi)->STATUS = SPI_STATUS_SLV_START_INTSTS_Msk ) |
#define SPI_CLR_UNIT_TRANS_INT_FLAG | ( | spi | ) | ( (spi)->STATUS = SPI_STATUS_IF_Msk ) |
#define SPI_DISABLE_3WIRE_MODE | ( | spi | ) | ( (spi)->CNTRL2 &= ~SPI_CNTRL2_NOSLVSEL_Msk ) |
#define SPI_DISABLE_BYTE_REORDER | ( | spi | ) | ( (spi)->CNTRL &= ~SPI_CNTRL_REORDER_Msk ) |
#define SPI_ENABLE_3WIRE_MODE | ( | spi | ) | ( (spi)->CNTRL2 |= SPI_CNTRL2_NOSLVSEL_Msk ) |
#define SPI_ENABLE_BYTE_REORDER | ( | spi | ) | ( (spi)->CNTRL |= SPI_CNTRL_REORDER_Msk ) |
#define SPI_GET_RX_FIFO_COUNT | ( | spi | ) | ( (((spi)->STATUS & SPI_STATUS_RX_FIFO_COUNT_Msk) >> SPI_STATUS_RX_FIFO_COUNT_Pos) & 0xf ) |
#define SPI_GET_RX_FIFO_EMPTY_FLAG | ( | spi | ) | ( ((spi)->STATUS & SPI_STATUS_RX_EMPTY_Msk) == SPI_STATUS_RX_EMPTY_Msk ? 1:0 ) |
#define SPI_GET_TX_FIFO_EMPTY_FLAG | ( | spi | ) | ( ((spi)->STATUS & SPI_STATUS_TX_EMPTY_Msk) == SPI_STATUS_TX_EMPTY_Msk ? 1:0 ) |
#define SPI_GET_TX_FIFO_FULL_FLAG | ( | spi | ) | ( ((spi)->STATUS & SPI_STATUS_TX_FULL_Msk) == SPI_STATUS_TX_FULL_Msk ? 1:0 ) |
#define SPI_IS_BUSY | ( | spi | ) | ( ((spi)->CNTRL & SPI_CNTRL_GO_BUSY_Msk) == SPI_CNTRL_GO_BUSY_Msk ? 1:0 ) |
#define SPI_READ_RX | ( | spi | ) | ( (spi)->RX ) |
#define SPI_SET_LSB_FIRST | ( | spi | ) | ( (spi)->CNTRL |= SPI_CNTRL_LSB_Msk ) |
#define SPI_SET_MSB_FIRST | ( | spi | ) | ( (spi)->CNTRL &= ~SPI_CNTRL_LSB_Msk ) |
#define SPI_SET_SUSPEND_CYCLE | ( | spi, | |
u32SuspCycle | |||
) | ( (spi)->CNTRL = ((spi)->CNTRL & ~SPI_CNTRL_SP_CYCLE_Msk) | (u32SuspCycle << SPI_CNTRL_SP_CYCLE_Pos) ) |
#define SPI_TRIGGER | ( | spi | ) | ( (spi)->CNTRL |= SPI_CNTRL_GO_BUSY_Msk ) |
#define SPI_WRITE_TX | ( | spi, | |
u32TxData | |||
) | ( (spi)->TX = u32TxData ) |
void SPI_ClearRxFIFO | ( | SPI_T * | spi | ) |
void SPI_ClearTxFIFO | ( | SPI_T * | spi | ) |
void SPI_Close | ( | SPI_T * | spi | ) |
void SPI_DisableAutoSS | ( | SPI_T * | spi | ) |
void SPI_DisableFIFO | ( | SPI_T * | spi | ) |
void SPI_DisableInt | ( | SPI_T * | spi, |
uint32_t | u32Mask | ||
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Disable FIFO related interrupts specified by u32Mask parameter.
spi | is the base address of SPI module. |
u32Mask | is the combination of all related interrupt enable bits. Each bit corresponds to a interrupt bit. This parameter decides which interrupts will be disabled. (SPI_IE_MASK, SPI_SSTA_INTEN_MASK, SPI_FIFO_TX_INTEN_MASK, SPI_FIFO_RX_INTEN_MASK, SPI_FIFO_RXOV_INTEN_MASK, SPI_FIFO_TIMEOUT_INTEN_MASK) |
void SPI_EnableAutoSS | ( | SPI_T * | spi, |
uint32_t | u32SSPinMask, | ||
uint32_t | u32ActiveLevel | ||
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Enable the automatic slave select function. Only available in Master mode.
spi | is the base address of SPI module. |
u32SSPinMask | specifies slave select pins. (SPI_SS) |
u32ActiveLevel | specifies the active level of slave select signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) |
void SPI_EnableFIFO | ( | SPI_T * | spi, |
uint32_t | u32TxThreshold, | ||
uint32_t | u32RxThreshold | ||
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void SPI_EnableInt | ( | SPI_T * | spi, |
uint32_t | u32Mask | ||
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Enable FIFO related interrupts specified by u32Mask parameter.
spi | is the base address of SPI module. |
u32Mask | is the combination of all related interrupt enable bits. Each bit corresponds to a interrupt bit. This parameter decides which interrupts will be enabled. (SPI_IE_MASK, SPI_SSTA_INTEN_MASK, SPI_FIFO_TX_INTEN_MASK, SPI_FIFO_RX_INTEN_MASK, SPI_FIFO_RXOV_INTEN_MASK, SPI_FIFO_TIMEOUT_INTEN_MASK) |
uint32_t SPI_GetBusClock | ( | SPI_T * | spi | ) |
uint32_t SPI_Open | ( | SPI_T * | spi, |
uint32_t | u32MasterSlave, | ||
uint32_t | u32SPIMode, | ||
uint32_t | u32DataWidth, | ||
uint32_t | u32BusClock | ||
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This function make SPI module be ready to transfer. By default, the SPI transfer sequence is MSB first and the automatic slave select function is disabled. In Slave mode, the u32BusClock must be NULL and the SPI clock divider setting will be 0.
spi | is the base address of SPI module. |
u32MasterSlave | decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) |
u32SPIMode | decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) |
u32DataWidth | decides the data width of a SPI transaction. |
u32BusClock | is the expected frequency of SPI bus clock in Hz. |
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uint32_t SPI_SetBusClock | ( | SPI_T * | spi, |
uint32_t | u32BusClock | ||
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