NUC029FAE_BSP V3.01.004
The Board Support Package for NUC029FAE MCU
Macros | Enumerator | Variables
Collaboration diagram for NUC029FAE Legacy Constants:

Macros

#define NULL   (0)
 NULL pointer. More...
 
#define TRUE   (1)
 Boolean true, define to use in API parameters or return value. More...
 
#define FALSE   (0)
 Boolean false, define to use in API parameters or return value. More...
 
#define ENABLE   (1)
 Enable, define to use in API parameters. More...
 
#define DISABLE   (0)
 Disable, define to use in API parameters. More...
 
#define BIT0   (0x00000001)
 Bit 0 mask of an 32 bit integer. More...
 
#define BIT1   (0x00000002)
 Bit 1 mask of an 32 bit integer. More...
 
#define BIT2   (0x00000004)
 Bit 2 mask of an 32 bit integer. More...
 
#define BIT3   (0x00000008)
 Bit 3 mask of an 32 bit integer. More...
 
#define BIT4   (0x00000010)
 Bit 4 mask of an 32 bit integer. More...
 
#define BIT5   (0x00000020)
 Bit 5 mask of an 32 bit integer. More...
 
#define BIT6   (0x00000040)
 Bit 6 mask of an 32 bit integer. More...
 
#define BIT7   (0x00000080)
 Bit 7 mask of an 32 bit integer. More...
 
#define BIT8   (0x00000100)
 Bit 8 mask of an 32 bit integer. More...
 
#define BIT9   (0x00000200)
 Bit 9 mask of an 32 bit integer. More...
 
#define BIT10   (0x00000400)
 Bit 10 mask of an 32 bit integer. More...
 
#define BIT11   (0x00000800)
 Bit 11 mask of an 32 bit integer. More...
 
#define BIT12   (0x00001000)
 Bit 12 mask of an 32 bit integer. More...
 
#define BIT13   (0x00002000)
 Bit 13 mask of an 32 bit integer. More...
 
#define BIT14   (0x00004000)
 Bit 14 mask of an 32 bit integer. More...
 
#define BIT15   (0x00008000)
 Bit 15 mask of an 32 bit integer. More...
 
#define BIT16   (0x00010000)
 Bit 16 mask of an 32 bit integer. More...
 
#define BIT17   (0x00020000)
 Bit 17 mask of an 32 bit integer. More...
 
#define BIT18   (0x00040000)
 Bit 18 mask of an 32 bit integer. More...
 
#define BIT19   (0x00080000)
 Bit 19 mask of an 32 bit integer. More...
 
#define BIT20   (0x00100000)
 Bit 20 mask of an 32 bit integer. More...
 
#define BIT21   (0x00200000)
 Bit 21 mask of an 32 bit integer. More...
 
#define BIT22   (0x00400000)
 Bit 22 mask of an 32 bit integer. More...
 
#define BIT23   (0x00800000)
 Bit 23 mask of an 32 bit integer. More...
 
#define BIT24   (0x01000000)
 Bit 24 mask of an 32 bit integer. More...
 
#define BIT25   (0x02000000)
 Bit 25 mask of an 32 bit integer. More...
 
#define BIT26   (0x04000000)
 Bit 26 mask of an 32 bit integer. More...
 
#define BIT27   (0x08000000)
 Bit 27 mask of an 32 bit integer. More...
 
#define BIT28   (0x10000000)
 Bit 28 mask of an 32 bit integer. More...
 
#define BIT29   (0x20000000)
 Bit 29 mask of an 32 bit integer. More...
 
#define BIT30   (0x40000000)
 Bit 30 mask of an 32 bit integer. More...
 
#define BIT31   (0x80000000)
 Bit 31 mask of an 32 bit integer. More...
 
#define BYTE0_Msk   (0x000000FF)
 Mask to get bit0~bit7 from a 32 bit integer. More...
 
#define BYTE1_Msk   (0x0000FF00)
 Mask to get bit8~bit15 from a 32 bit integer. More...
 
#define BYTE2_Msk   (0x00FF0000)
 Mask to get bit16~bit23 from a 32 bit integer. More...
 
#define BYTE3_Msk   (0xFF000000)
 Mask to get bit24~bit31 from a 32 bit integer. More...
 
#define GET_BYTE0(u32Param)   ((u32Param & BYTE0_Msk) )
 
#define GET_BYTE1(u32Param)   ((u32Param & BYTE1_Msk) >> 8)
 
#define GET_BYTE2(u32Param)   ((u32Param & BYTE2_Msk) >> 16)
 
#define GET_BYTE3(u32Param)   ((u32Param & BYTE3_Msk) >> 24)
 

Variables

__IO uint32_t ACMP_T::CMPCR [2]
 
__IO uint32_t ACMP_T::CMPSR
 
__IO uint32_t ACMP_T::CMPRVCR
 
__IO uint32_t CLK_T::PWRCON
 
__IO uint32_t CLK_T::AHBCLK
 
__IO uint32_t CLK_T::APBCLK
 
__IO uint32_t CLK_T::CLKSTATUS
 
__IO uint32_t CLK_T::CLKSEL0
 
__IO uint32_t CLK_T::CLKSEL1
 
__IO uint32_t CLK_T::CLKDIV
 
__IO uint32_t CLK_T::CLKSEL2
 
uint32_t CLK_T::RESERVED0
 
__IO uint32_t CLK_T::FRQDIV
 
__IO uint32_t ADC_T::ADDR
 
uint32_t ADC_T::RESERVED0 [7]
 
__IO uint32_t ADC_T::ADCR
 
__IO uint32_t ADC_T::ADCHER
 
__IO uint32_t ADC_T::ADCMPR [2]
 
__IO uint32_t ADC_T::ADSR
 
__IO uint32_t ADC_T::ADTDCR
 
__IO uint32_t ADC_T::ADSAMP
 
__IO uint32_t FMC_T::ISPCON
 
__IO uint32_t FMC_T::ISPADR
 
__IO uint32_t FMC_T::ISPDAT
 
__IO uint32_t FMC_T::ISPCMD
 
__IO uint32_t FMC_T::ISPTRG
 
__I uint32_t FMC_T::DFBADR
 
__IO uint32_t GPIO_T::PMD
 
__IO uint32_t GPIO_T::OFFD
 
__IO uint32_t GPIO_T::DOUT
 
__IO uint32_t GPIO_T::DMASK
 
__I uint32_t GPIO_T::PIN
 
__IO uint32_t GPIO_T::DBEN
 
__IO uint32_t GPIO_T::IMD
 
__IO uint32_t GPIO_T::IEN
 
__IO uint32_t GPIO_T::ISRC
 
__IO uint32_t GPIO_DBNCECON_T::DBNCECON
 
__IO uint32_t GPIOBIT_T::GP_BIT0
 
__IO uint32_t GPIOBIT_T::GP_BIT1
 
__IO uint32_t GPIOBIT_T::GP_BIT2
 
__IO uint32_t GPIOBIT_T::GP_BIT3
 
__IO uint32_t GPIOBIT_T::GP_BIT4
 
__IO uint32_t GPIOBIT_T::GP_BIT5
 
__IO uint32_t GPIOBIT_T::GP_BIT6
 
__IO uint32_t GPIOBIT_T::GP_BIT7
 
__IO uint32_t I2C_T::I2CON
 
__IO uint32_t I2C_T::I2CADDR0
 
__IO uint32_t I2C_T::I2CDAT
 
__IO uint32_t I2C_T::I2CSTATUS
 
__IO uint32_t I2C_T::I2CLK
 
__IO uint32_t I2C_T::I2CTOC
 
__IO uint32_t I2C_T::I2CADDR1
 
__IO uint32_t I2C_T::I2CADDR2
 
__IO uint32_t I2C_T::I2CADDR3
 
__IO uint32_t I2C_T::I2CADM0
 
__IO uint32_t I2C_T::I2CADM1
 
__IO uint32_t I2C_T::I2CADM2
 
__IO uint32_t I2C_T::I2CADM3
 
uint32_t I2C_T::RESERVED0
 
uint32_t I2C_T::RESERVED1
 
__IO uint32_t I2C_T::I2CON2
 
__IO uint32_t I2C_T::I2CSTATUS2
 
__I uint32_t INT_T::IRQSRC [32]
 
__IO uint32_t INT_T::NMICNO
 
__IO uint32_t INT_T::MCUIRQ
 
__IO uint32_t PWM_T::PPR
 
__IO uint32_t PWM_T::CSR
 
__IO uint32_t PWM_T::PCR
 
__IO uint32_t PWM_T::CNR [6]
 
__IO uint32_t PWM_T::CMR [6]
 
uint32_t PWM_T::RESERVED0 [6]
 
__IO uint32_t PWM_T::PIER
 
__IO uint32_t PWM_T::PIIR
 
__IO uint32_t PWM_T::POE
 
__IO uint32_t PWM_T::PFBCON
 
__IO uint32_t PWM_T::PDZIR
 
__IO uint32_t PWM_T::TRGCON0
 
__IO uint32_t PWM_T::TRGCON1
 
__IO uint32_t PWM_T::TRGSTS0
 
__IO uint32_t PWM_T::TRGSTS1
 
__IO uint32_t PWM_T::PHCHG
 
__IO uint32_t PWM_T::PHCHGNXT
 
__IO uint32_t PWM_T::PHCHGMASK
 
__IO uint32_t PWM_T::INTACCUCTL
 
__IO uint32_t SPI_T::CNTRL
 
__IO uint32_t SPI_T::DIVIDER
 
__IO uint32_t SPI_T::SSR
 
uint32_t SPI_T::RESERVED0
 
__I uint32_t SPI_T::RX
 
uint32_t SPI_T::RESERVED1 [3]
 
__O uint32_t SPI_T::TX
 
uint32_t SPI_T::RESERVED2 [6]
 
__IO uint32_t SPI_T::CNTRL2
 
__IO uint32_t SPI_T::FIFO_CTL
 
__IO uint32_t SPI_T::STATUS
 
__I uint32_t SYS_T::PDID
 
__IO uint32_t SYS_T::RSTSRC
 
__IO uint32_t SYS_T::IPRSTC1
 
__IO uint32_t SYS_T::IPRSTC2
 
uint32_t SYS_T::RESERVED0 [2]
 
__IO uint32_t SYS_T::BODCTL
 
uint32_t SYS_T::RESERVED1 [5]
 
__IO uint32_t SYS_T::P0_MFP
 
__IO uint32_t SYS_T::P1_MFP
 
__IO uint32_t SYS_T::P2_MFP
 
__IO uint32_t SYS_T::P3_MFP
 
__IO uint32_t SYS_T::P4_MFP
 
__IO uint32_t SYS_T::P5_MFP
 
uint32_t SYS_T::RESERVED3 [14]
 
__IO uint32_t SYS_T::IRCTRIMCTL
 
__IO uint32_t SYS_T::IRCTRIMIER
 
__IO uint32_t SYS_T::IRCTRIMISR
 
uint32_t SYS_T::RESERVED4 [29]
 
__IO uint32_t SYS_T::RegLockAddr
 
__IO uint32_t TIMER_T::TCSR
 
__IO uint32_t TIMER_T::TCMPR
 
__IO uint32_t TIMER_T::TISR
 
__I uint32_t TIMER_T::TDR
 
__I uint32_t TIMER_T::TCAP
 
__IO uint32_t TIMER_T::TEXCON
 
__IO uint32_t TIMER_T::TEXISR
 
__I uint32_t   UART_T::RBR
 
__O uint32_t   UART_T::THR
 
union {
   __I uint32_t   UART_T::RBR
 
   __O uint32_t   UART_T::THR
 
}; 
 
__IO uint32_t UART_T::IER
 
__IO uint32_t UART_T::FCR
 
__IO uint32_t UART_T::LCR
 
__IO uint32_t UART_T::MCR
 
__IO uint32_t UART_T::MSR
 
__IO uint32_t UART_T::FSR
 
__IO uint32_t UART_T::ISR
 
__IO uint32_t UART_T::TOR
 
__IO uint32_t UART_T::BAUD
 
__IO uint32_t UART_T::IRCR
 
__IO uint32_t UART_T::ALT_CSR
 
__IO uint32_t UART_T::FUN_SEL
 
__IO uint32_t WDT_T::WTCR
 

Detailed Description

NUC029FAE Legacy Constants

Macro Definition Documentation

◆ BIT0

#define BIT0   (0x00000001)

Bit 0 mask of an 32 bit integer.

Definition at line 3399 of file NUC029FAE.h.

◆ BIT1

#define BIT1   (0x00000002)

Bit 1 mask of an 32 bit integer.

Definition at line 3400 of file NUC029FAE.h.

◆ BIT10

#define BIT10   (0x00000400)

Bit 10 mask of an 32 bit integer.

Definition at line 3409 of file NUC029FAE.h.

◆ BIT11

#define BIT11   (0x00000800)

Bit 11 mask of an 32 bit integer.

Definition at line 3410 of file NUC029FAE.h.

◆ BIT12

#define BIT12   (0x00001000)

Bit 12 mask of an 32 bit integer.

Definition at line 3411 of file NUC029FAE.h.

◆ BIT13

#define BIT13   (0x00002000)

Bit 13 mask of an 32 bit integer.

Definition at line 3412 of file NUC029FAE.h.

◆ BIT14

#define BIT14   (0x00004000)

Bit 14 mask of an 32 bit integer.

Definition at line 3413 of file NUC029FAE.h.

◆ BIT15

#define BIT15   (0x00008000)

Bit 15 mask of an 32 bit integer.

Definition at line 3414 of file NUC029FAE.h.

◆ BIT16

#define BIT16   (0x00010000)

Bit 16 mask of an 32 bit integer.

Definition at line 3415 of file NUC029FAE.h.

◆ BIT17

#define BIT17   (0x00020000)

Bit 17 mask of an 32 bit integer.

Definition at line 3416 of file NUC029FAE.h.

◆ BIT18

#define BIT18   (0x00040000)

Bit 18 mask of an 32 bit integer.

Definition at line 3417 of file NUC029FAE.h.

◆ BIT19

#define BIT19   (0x00080000)

Bit 19 mask of an 32 bit integer.

Definition at line 3418 of file NUC029FAE.h.

◆ BIT2

#define BIT2   (0x00000004)

Bit 2 mask of an 32 bit integer.

Definition at line 3401 of file NUC029FAE.h.

◆ BIT20

#define BIT20   (0x00100000)

Bit 20 mask of an 32 bit integer.

Definition at line 3419 of file NUC029FAE.h.

◆ BIT21

#define BIT21   (0x00200000)

Bit 21 mask of an 32 bit integer.

Definition at line 3420 of file NUC029FAE.h.

◆ BIT22

#define BIT22   (0x00400000)

Bit 22 mask of an 32 bit integer.

Definition at line 3421 of file NUC029FAE.h.

◆ BIT23

#define BIT23   (0x00800000)

Bit 23 mask of an 32 bit integer.

Definition at line 3422 of file NUC029FAE.h.

◆ BIT24

#define BIT24   (0x01000000)

Bit 24 mask of an 32 bit integer.

Definition at line 3423 of file NUC029FAE.h.

◆ BIT25

#define BIT25   (0x02000000)

Bit 25 mask of an 32 bit integer.

Definition at line 3424 of file NUC029FAE.h.

◆ BIT26

#define BIT26   (0x04000000)

Bit 26 mask of an 32 bit integer.

Definition at line 3425 of file NUC029FAE.h.

◆ BIT27

#define BIT27   (0x08000000)

Bit 27 mask of an 32 bit integer.

Definition at line 3426 of file NUC029FAE.h.

◆ BIT28

#define BIT28   (0x10000000)

Bit 28 mask of an 32 bit integer.

Definition at line 3427 of file NUC029FAE.h.

◆ BIT29

#define BIT29   (0x20000000)

Bit 29 mask of an 32 bit integer.

Definition at line 3428 of file NUC029FAE.h.

◆ BIT3

#define BIT3   (0x00000008)

Bit 3 mask of an 32 bit integer.

Definition at line 3402 of file NUC029FAE.h.

◆ BIT30

#define BIT30   (0x40000000)

Bit 30 mask of an 32 bit integer.

Definition at line 3429 of file NUC029FAE.h.

◆ BIT31

#define BIT31   (0x80000000)

Bit 31 mask of an 32 bit integer.

Definition at line 3430 of file NUC029FAE.h.

◆ BIT4

#define BIT4   (0x00000010)

Bit 4 mask of an 32 bit integer.

Definition at line 3403 of file NUC029FAE.h.

◆ BIT5

#define BIT5   (0x00000020)

Bit 5 mask of an 32 bit integer.

Definition at line 3404 of file NUC029FAE.h.

◆ BIT6

#define BIT6   (0x00000040)

Bit 6 mask of an 32 bit integer.

Definition at line 3405 of file NUC029FAE.h.

◆ BIT7

#define BIT7   (0x00000080)

Bit 7 mask of an 32 bit integer.

Definition at line 3406 of file NUC029FAE.h.

◆ BIT8

#define BIT8   (0x00000100)

Bit 8 mask of an 32 bit integer.

Definition at line 3407 of file NUC029FAE.h.

◆ BIT9

#define BIT9   (0x00000200)

Bit 9 mask of an 32 bit integer.

Definition at line 3408 of file NUC029FAE.h.

◆ BYTE0_Msk

#define BYTE0_Msk   (0x000000FF)

Mask to get bit0~bit7 from a 32 bit integer.

Definition at line 3433 of file NUC029FAE.h.

◆ BYTE1_Msk

#define BYTE1_Msk   (0x0000FF00)

Mask to get bit8~bit15 from a 32 bit integer.

Definition at line 3434 of file NUC029FAE.h.

◆ BYTE2_Msk

#define BYTE2_Msk   (0x00FF0000)

Mask to get bit16~bit23 from a 32 bit integer.

Definition at line 3435 of file NUC029FAE.h.

◆ BYTE3_Msk

#define BYTE3_Msk   (0xFF000000)

Mask to get bit24~bit31 from a 32 bit integer.

Definition at line 3436 of file NUC029FAE.h.

◆ DISABLE

#define DISABLE   (0)

Disable, define to use in API parameters.

Definition at line 3396 of file NUC029FAE.h.

◆ ENABLE

#define ENABLE   (1)

Enable, define to use in API parameters.

Definition at line 3395 of file NUC029FAE.h.

◆ FALSE

#define FALSE   (0)

Boolean false, define to use in API parameters or return value.

Definition at line 3393 of file NUC029FAE.h.

◆ GET_BYTE0

#define GET_BYTE0 (   u32Param)    ((u32Param & BYTE0_Msk) )

Extract Byte 0 (Bit 0~ 7) from parameter u32Param

Definition at line 3438 of file NUC029FAE.h.

◆ GET_BYTE1

#define GET_BYTE1 (   u32Param)    ((u32Param & BYTE1_Msk) >> 8)

Extract Byte 1 (Bit 8~15) from parameter u32Param

Definition at line 3439 of file NUC029FAE.h.

◆ GET_BYTE2

#define GET_BYTE2 (   u32Param)    ((u32Param & BYTE2_Msk) >> 16)

Extract Byte 2 (Bit 16~23) from parameter u32Param

Definition at line 3440 of file NUC029FAE.h.

◆ GET_BYTE3

#define GET_BYTE3 (   u32Param)    ((u32Param & BYTE3_Msk) >> 24)

Extract Byte 3 (Bit 24~31) from parameter u32Param

Definition at line 3441 of file NUC029FAE.h.

◆ NULL

#define NULL   (0)

NULL pointer.

Definition at line 3389 of file NUC029FAE.h.

◆ TRUE

#define TRUE   (1)

Boolean true, define to use in API parameters or return value.

Definition at line 3392 of file NUC029FAE.h.

Variable Documentation

◆ 

union { ... } UART_T::@1

◆ ADCHER

__IO uint32_t ADC_T::ADCHER

Offset: 0x0024 A/D Channel Enable Register

Definition at line 647 of file NUC029FAE.h.

◆ ADCMPR

__IO uint32_t ADC_T::ADCMPR[2]

Offset: 0x0028, 0x002C A/D Compare Register 0 & 1

Definition at line 648 of file NUC029FAE.h.

◆ ADCR

__IO uint32_t ADC_T::ADCR

Offset: 0x0020 A/D Control Register

Definition at line 646 of file NUC029FAE.h.

◆ ADDR

__IO uint32_t ADC_T::ADDR

Offset: 0x0000 A/D Data Register

Definition at line 644 of file NUC029FAE.h.

◆ ADSAMP

__IO uint32_t ADC_T::ADSAMP

Offset: 0x0048 ADC Sampling Time Counter Register

Definition at line 651 of file NUC029FAE.h.

◆ ADSR

__IO uint32_t ADC_T::ADSR

Offset: 0x0030 A/D Status Register

Definition at line 649 of file NUC029FAE.h.

◆ ADTDCR

__IO uint32_t ADC_T::ADTDCR

Offset: 0x0044 A/D Trigger Delay Control Register

Definition at line 650 of file NUC029FAE.h.

◆ AHBCLK

__IO uint32_t CLK_T::AHBCLK

AHBCLK

Offset: 0x04 AHB Devices Clock Enable Control Register

Bits Field Descriptions
[2] ISP_EN Flash ISP Controller Clock Enable Control.
1 = To enable the Flash ISP controller clock.
0 = To disable the Flash ISP controller clock.

Definition at line 270 of file NUC029FAE.h.

◆ ALT_CSR

__IO uint32_t UART_T::ALT_CSR

Offset: 0x002C UART Alternate Control/Status Register

Definition at line 2884 of file NUC029FAE.h.

◆ APBCLK

__IO uint32_t CLK_T::APBCLK

APBCLK

Offset: 0x08 APB Devices Clock Enable Control Register

Bits Field Descriptions
[0] WDT_EN Watch Dog Timer Clock Enable.
This bit is the protected bit, program this need a open lock sequence, write "59h","16h","88h" to
address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address
SYS_BA + 0x100
0 = Disable Watchdog Timer Clock
1 = Enable Watchdog Timer Clock
[2] TMR0_EN Timer0 Clock Enable Control
0 = Disable Timer0 Clock
1 = Enable Timer0 Clock
[3] TMR1_EN Timer1 Clock Enable Control
0 = Disable Timer1 Clock
1 = Enable Timer1 Clock
[6] FDIV_EN Clock Divider Clock Enable Control
0 = Disable FDIV Clock
1 = Enable FDIV Clock
[8] I2C_EN I2C Clock Enable Control.
0 = Disable I2C Clock
1 = Enable I2C Clock
[12] SPI_EN SPI Clock Enable Control.
0 = Disable SPI Clock
1 = Enable SPI Clock
[16] UART_EN UART Clock Enable Control.
1 = Enable UART clock
0 = Disable UART clock
[20] PWM01_EN PWM_01 Clock Enable Control.
1 = Enable PWM01 clock
0 = Disable PWM01 clock
[21] PWM23_EN PWM_23 Clock Enable Control.
1 = Enable PWM23 clock
0 = Disable PWM23 clock
[22] PWM45_EN PWM_45 Clock Enable Control.
1 = Enable PWM45 clock
0 = Disable PWM45 clock
[28] ADC_EN Analog-Digital-Converter (ADC) Clock Enable Control.
1 = Enable ADC clock
0 = Disable ADC clock
[30] CMP_EN Comparator Clock Enable Control.
1 = Enable Analog Comparator clock
0 = Disable Analog Comparator clock

Definition at line 319 of file NUC029FAE.h.

◆ BAUD

__IO uint32_t UART_T::BAUD

Offset: 0x0024 UART Baud Rate Divisor Register

Definition at line 2882 of file NUC029FAE.h.

◆ BODCTL

__IO uint32_t SYS_T::BODCTL

BODCR

Offset: 0x18 Brown-Out Detector Control Register

Bits Field Descriptions
[2:1] BOD_VL Brown Out Detector Threshold Voltage Selection (initiated & write-protected bit)
The default value is set by flash controller user configuration register config0 bit[22:21]
Brown out voltage
11 = Disable 2.7V and 3.8V
10 = 3.8V
01 = 2.7V
00 = Reserved
[3] BOD_RSTEN Brown Out Reset Enable (initiated & write-protected bit)
1= Enable the Brown Out "RESET" function, when the Brown Out Detector function is enable
and the detected voltage is lower than the threshold then assert a signal to reset the chip
The default value is set by flash controller user configuration register config0 bit[20]
0= Enable the Brown Out "INTERRUPT" function, when the Brown Out Detector function is
enable and the detected voltage is lower than the threshold then assert a signal to interrupt
the MCU Cortex-M0
When the BOD_EN is enabled and the interrupt is assert, the interrupt will keep till to the
BOD_EN set to "0". The interrupt for CPU can be blocked by disable the NVIC in CPU for BOD
interrupt or disable the interrupt source by disable the BOD_EN and then re-enable the BOD_EN
function if the BOD function is required
[4] BOD_INTF Brown Out Detector Interrupt Flag
1= When Brown Out Detector detects the VDD is dropped through the voltage of BOD_VL setting
or the VDD is raised up through the voltage of BOD_VL setting, this bit is set to "1" and the
brown out interrupt is requested if brown out interrupt is enabled.
0= Brown Out Detector does not detect any voltage draft at VDD down through or up through the
voltage of BOD_VL setting.
[6] BOD_OUT The status for Brown Out Detector output state
1= Brown Out Detector status output is 1, the detected voltage is lower than BOD_VL setting. If
the BOD_EN is "0"(disabled), this bit always response "0"
0= Brown Out Detector status output is 0, the detected voltage is higher than BOD_VL setting

Definition at line 2156 of file NUC029FAE.h.

◆ CLKDIV

__IO uint32_t CLK_T::CLKDIV

CLKDIV

Offset: 0x18 Clock Divider Number Register

Bits Field Descriptions
[3:0] HCLK_N HCLK clock divide number from HCLK clock source
The HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1)
[11:8] UART_N UART clock divide number from UART clock source
The UART clock frequency = (UART clock source frequency ) / (UART_N + 1)
[23:16] ADC_N ADC clock divide number from ADC clock source
The ADC clock frequency = (ADC clock source frequency ) / (ADC_N + 1)

Definition at line 433 of file NUC029FAE.h.

◆ CLKSEL0

__IO uint32_t CLK_T::CLKSEL0

CLKSEL0

Offset: 0x10 Clock Source Select Control Register 0

Bits Field Descriptions
[2:0] HCLK_S HCLK clock source select.
Note:
1. Before clock switch the related clock sources (pre-select and new-select) must be turn on
2. These bits are protected bit, program this need an open lock sequence, write
"59h","16h","88h" to address 0x5000_0100 to un-lock this bit. Reference the register
REGWRPROT at address SYS_BA + 0x100
3. To set PWRCON[1:0] to select 12 MHz or 32 KHz crystal clock.
000 = Clock source from external 12 MHz or 32 KHz crystal clock.
011 = clock source from internal 10KHz oscillator clock
111 = clock source from internal 22.1184 MHz oscillator clock
others = Reserved
[5:3] STCLK_S MCU Cortex_M0 SysTick clock source select.
These bits are protected bit, program this need an open lock sequence, write "59h","16h","88h" to
address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address SYS_BA
+ 0x100
000 = Clock source from 12 MHz or 32 KHz crystal clock
010 = Clock source from 12 MHz or 32 KHz crystal clock/2
011 = clock source from HCLK/2
111 = clock source from internal 22.1184 MHz oscillator clock/2
others = Reserved
Note: To set PWRCON[1:0] to select 12 MHz or 32 KHz crystal clock.

Definition at line 373 of file NUC029FAE.h.

◆ CLKSEL1

__IO uint32_t CLK_T::CLKSEL1

CLKSEL1

Offset: 0x14 Clock Source Select Control Register 1

Bits Field Descriptions
[1:0] WDT_S Watchdog Timer clock source select.
These bits are protected bit, program this need a open lock sequence, write "59h","16h","88h" to
address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address
SYS_BA + 0x100
00 = Clock source from external 12 MHz or 32 KHz crystal clock.
10 = clock source from HCLK/2048 clock
11 = clock source from internal 10KHz oscillator clock
[3:2] ADC_S ADC clock source select.
00 = Clock source from external 12 MHz or 32 KHz crystal clock.
10 = clock source from HCLK
11 = clock source from internal 22.1184 MHz oscillator clock
[10:8] TMR0_S TIMER0 clock source select.
000 = Clock source from external 12 MHz or 32 KHz crystal clock
001 = Clock source from internal 10 KHz oscillator clock.
010 = clock source from HCLK
011 = clock source from external trigger
111 = clock source from internal 22.1184 MHz oscillator clock
[14:12] TMR1_S TIMER1 clock source select.
000 = Clock source from external 12 MHz or 32 KHz crystal clock
001 = Clock source from internal 10 KHz oscillator clock.
010 = clock source from HCLK
011 = clock source from external trigger
111 = clock source from internal 22.1184 MHz oscillator clock
[25:24] UART_S UART clock source select.
00 = Clock source from external 12 MHz or 32 KHz crystal clock
10 = clock source from internal 22.1184 MHz oscillator clock
[29:28] PWM01_S PWM0 and PWM1 clock source select.
PWM0 and PWM1 uses the same Engine clock source, both of them with the same pre-scalar
10 = clock source from HCLK
others = Reserved
[31:30] PWM23_S PWM2 and PWM3 clock source select.
PWM2 and PWM3 uses the same Engine clock source, both of them with the same pre-scalar
10 = clock source from HCLK
others = Reserved

Definition at line 417 of file NUC029FAE.h.

◆ CLKSEL2

__IO uint32_t CLK_T::CLKSEL2

CLKSEL2

Offset: 0x1C Clock Source Select Control Register 2

Bits Field Descriptions
[3:2] FRQDIV_S Clock Divider Clock Source Select
00 = Clock source from external 12 MHz or 32 KHz crystal clock
10 = clock source from HCLK
11 = clock source from internal 22.1184 MHz oscillator clock
[5:4] PWM45_S PWM4 and PWM5 clock source select. - PWM4 and PWM5 used the same Engine clock source,
both of them with the same pre-scalar
10 = clock source from HCLK
others = Reserved

Definition at line 451 of file NUC029FAE.h.

◆ CLKSTATUS

__IO uint32_t CLK_T::CLKSTATUS

CLKSTATUS

Offset: 0x0C Clock Status Monitor Register

Bits Field Descriptions
[0] XTL_STB XTL12M or XTL32K clock source stable flag
1 = External Crystal clock is stable
0 = External Crystal clock is not stable or not enable
[3] OSC10K_STB OSC10K clock source stable flag
1 = OSC10K clock is stable
0 = OSC10K clock is not stable or not enable
[4] OSC22M_STB OSC22M clock source stable flag
1 = OSC22M clock is stable
0 = OSC22M clock is not stable or not enable
[7] CLK_SW_FAIL Clock switch fail flag
1 = Clock switch fail
0 = Clock switch success
This bit will be set when target switch clock source is not stable. Write 1 to clear this bit to zero.

Definition at line 342 of file NUC029FAE.h.

◆ CMPCR

__IO uint32_t ACMP_T::CMPCR[2]

Offset: 0x0000, 0x0004 Comparator Control 0 & 1

Definition at line 148 of file NUC029FAE.h.

◆ CMPRVCR

__IO uint32_t ACMP_T::CMPRVCR

Offset: 0x000C Comparator Reference Voltage Control Register

Definition at line 150 of file NUC029FAE.h.

◆ CMPSR

__IO uint32_t ACMP_T::CMPSR

Offset: 0x0008 Comparator Status Register

Definition at line 149 of file NUC029FAE.h.

◆ CMR

__IO uint32_t PWM_T::CMR[6]

Offset: 0x0024 ~ 0x0038 PWM Comparator Register 0 ~ 5

Definition at line 1177 of file NUC029FAE.h.

◆ CNR

__IO uint32_t PWM_T::CNR[6]

Offset: 0x000C ~ 0x0020 PWM Counter Register 0 ~ 5

Definition at line 1176 of file NUC029FAE.h.

◆ CNTRL

__IO uint32_t SPI_T::CNTRL

Offset: 0x0000 SPI Control and Status Register

Definition at line 1823 of file NUC029FAE.h.

◆ CNTRL2

__IO uint32_t SPI_T::CNTRL2

Offset: 0x003C SPI Control and Status Register 2

Definition at line 1831 of file NUC029FAE.h.

◆ CSR

__IO uint32_t PWM_T::CSR

Offset: 0x0004 PWM Clock Select Register

Definition at line 1174 of file NUC029FAE.h.

◆ DBEN

__IO uint32_t GPIO_T::DBEN

Offset: 0x0014 GPIO Port De-bounce Enable

Definition at line 935 of file NUC029FAE.h.

◆ DBNCECON

__IO uint32_t GPIO_DBNCECON_T::DBNCECON

Offset: 0x0000 GPIO De-bounce Cycle Control Register

Definition at line 944 of file NUC029FAE.h.

◆ DFBADR

__I uint32_t FMC_T::DFBADR

DFBADR

Offset: 0x14 Data Flash Base Address Register

Bits Field Descriptions
[31:0] DFBA Data Flash Base Address
This register indicates data flash start address. It is a read only register.

| | | | | |It is a read only register. | | | | | |The data flash start address is defined by user. Since on chip flash erase | | |unit is 512 bytes, it is mandatory to keep bit 8-0 as "0".

Definition at line 881 of file NUC029FAE.h.

◆ DIVIDER

__IO uint32_t SPI_T::DIVIDER

Offset: 0x0004 SPI Clock Divider Register

Definition at line 1824 of file NUC029FAE.h.

◆ DMASK

__IO uint32_t GPIO_T::DMASK

Offset: 0x000C GPIO Port Data Output Write Mask

Definition at line 933 of file NUC029FAE.h.

◆ DOUT

__IO uint32_t GPIO_T::DOUT

Offset: 0x0008 GPIO Port Data Output

Definition at line 932 of file NUC029FAE.h.

◆ FCR

__IO uint32_t UART_T::FCR

Offset: 0x0008 UART FIFO Control Register

Definition at line 2875 of file NUC029FAE.h.

◆ FIFO_CTL

__IO uint32_t SPI_T::FIFO_CTL

Offset: 0x0040 SPI FIFO Control Register

Definition at line 1832 of file NUC029FAE.h.

◆ FRQDIV

__IO uint32_t CLK_T::FRQDIV

FRQDIV

Offset: 0x24 Frequency Divider Control Register

Bits Field Descriptions
[3:0] FSEL Divider Output Frequency Selection Bits
The formula of output frequency is
Fout = Fin/2^(N+1),
where Fin is the input clock frequency, Fout is the frequency of divider output clock, N is the 4-bit
value of FSEL[3:0].
[4] DIVIDER_EN Frequency Divider Enable Bit
0 = Disable Frequency Divider
1 = Enable Frequency Divider

Definition at line 473 of file NUC029FAE.h.

◆ FSR

__IO uint32_t UART_T::FSR

Offset: 0x0018 UART FIFO Status Register

Definition at line 2879 of file NUC029FAE.h.

◆ FUN_SEL

__IO uint32_t UART_T::FUN_SEL

Offset: 0x0030 UART Function Select Register

Definition at line 2885 of file NUC029FAE.h.

◆ GP_BIT0

__IO uint32_t GPIOBIT_T::GP_BIT0

Offset: 0x0000 Px.0 Data Output Value

Definition at line 1020 of file NUC029FAE.h.

◆ GP_BIT1

__IO uint32_t GPIOBIT_T::GP_BIT1

Offset: 0x0004 Px.1 Data Output Value

Definition at line 1021 of file NUC029FAE.h.

◆ GP_BIT2

__IO uint32_t GPIOBIT_T::GP_BIT2

Offset: 0x0008 Px.2 Data Output Value

Definition at line 1022 of file NUC029FAE.h.

◆ GP_BIT3

__IO uint32_t GPIOBIT_T::GP_BIT3

Offset: 0x000C Px.3 Data Output Value

Definition at line 1023 of file NUC029FAE.h.

◆ GP_BIT4

__IO uint32_t GPIOBIT_T::GP_BIT4

Offset: 0x0010 Px.4 Data Output Value

Definition at line 1024 of file NUC029FAE.h.

◆ GP_BIT5

__IO uint32_t GPIOBIT_T::GP_BIT5

Offset: 0x0014 Px.5 Data Output Value

Definition at line 1025 of file NUC029FAE.h.

◆ GP_BIT6

__IO uint32_t GPIOBIT_T::GP_BIT6

Offset: 0x0018 Px.6 Data Output Value

Definition at line 1026 of file NUC029FAE.h.

◆ GP_BIT7

__IO uint32_t GPIOBIT_T::GP_BIT7

Offset: 0x001C Px.7 Data Output Value

Definition at line 1027 of file NUC029FAE.h.

◆ I2CADDR0

__IO uint32_t I2C_T::I2CADDR0

Offset: 0x0004 I2C Slave Address Register 0

Definition at line 1043 of file NUC029FAE.h.

◆ I2CADDR1

__IO uint32_t I2C_T::I2CADDR1

Offset: 0x0018 I2C Slave Address Register 1

Definition at line 1048 of file NUC029FAE.h.

◆ I2CADDR2

__IO uint32_t I2C_T::I2CADDR2

Offset: 0x001C I2C Slave Address Register 2

Definition at line 1049 of file NUC029FAE.h.

◆ I2CADDR3

__IO uint32_t I2C_T::I2CADDR3

Offset: 0x0020 I2C Slave Address Register 3

Definition at line 1050 of file NUC029FAE.h.

◆ I2CADM0

__IO uint32_t I2C_T::I2CADM0

Offset: 0x0024 I2C Slave Address Mask Register 0

Definition at line 1051 of file NUC029FAE.h.

◆ I2CADM1

__IO uint32_t I2C_T::I2CADM1

Offset: 0x0028 I2C Slave Address Mask Register 1

Definition at line 1052 of file NUC029FAE.h.

◆ I2CADM2

__IO uint32_t I2C_T::I2CADM2

Offset: 0x002C I2C Slave Address Mask Register 2

Definition at line 1053 of file NUC029FAE.h.

◆ I2CADM3

__IO uint32_t I2C_T::I2CADM3

Offset: 0x0030 I2C Slave Address Mask Register 3

Definition at line 1054 of file NUC029FAE.h.

◆ I2CDAT

__IO uint32_t I2C_T::I2CDAT

Offset: 0x0008 I2C Data Register

Definition at line 1044 of file NUC029FAE.h.

◆ I2CLK

__IO uint32_t I2C_T::I2CLK

Offset: 0x0010 I2C Clock Divided Register

Definition at line 1046 of file NUC029FAE.h.

◆ I2CON

__IO uint32_t I2C_T::I2CON

Offset: 0x0000 I2C Control Register

Definition at line 1042 of file NUC029FAE.h.

◆ I2CON2

__IO uint32_t I2C_T::I2CON2

Offset: 0x003C I2C Control Register 2

Definition at line 1057 of file NUC029FAE.h.

◆ I2CSTATUS

__IO uint32_t I2C_T::I2CSTATUS

Offset: 0x000C I2C Status Register

Definition at line 1045 of file NUC029FAE.h.

◆ I2CSTATUS2

__IO uint32_t I2C_T::I2CSTATUS2

Offset: 0x0040 I2C Status Register 2

Definition at line 1058 of file NUC029FAE.h.

◆ I2CTOC

__IO uint32_t I2C_T::I2CTOC

Offset: 0x0014 I2C Time-Out Counter Register

Definition at line 1047 of file NUC029FAE.h.

◆ IEN

__IO uint32_t GPIO_T::IEN

Offset: 0x001C GPIO Port Interrupt Enable

Definition at line 937 of file NUC029FAE.h.

◆ IER

__IO uint32_t UART_T::IER

Offset: 0x0004 UART Interrupt Enable Register

Definition at line 2874 of file NUC029FAE.h.

◆ IMD

__IO uint32_t GPIO_T::IMD

Offset: 0x0018 GPIO Port Interrupt Mode Select

Definition at line 936 of file NUC029FAE.h.

◆ INTACCUCTL

__IO uint32_t PWM_T::INTACCUCTL

Offset: 0x0084 PWM Period Interrupt Accumulation Control Register

Definition at line 1191 of file NUC029FAE.h.

◆ IPRSTC1

__IO uint32_t SYS_T::IPRSTC1

IPRSTC1

Offset: 0x08 Peripheral Reset Control Resister 1

Bits Field Descriptions
[0] CHIP_RST CHIP one shot reset.
Set this bit will reset the CHIP, including CPU kernel and all peripherals, and this bit will
automatically return to "0" after the 2 clock cycles.
The CHIP_RST is same as the POR reset , all the chip module is reset and the chip setting from
flash are also reload
This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to
address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address SYS_BA
+ 0x100
0= Normal
1= Reset CHIP
[1] CPU_RST CPU kernel one shot reset.
Set this bit will reset the Cortex-M0 CPU kernel and Flash memory controller (FMC). This bit will
automatically return to "0" after the 2 clock cycles
This bit is the protected bit, program this need an open lock sequence, write "59h","16h","88h" to
address 0x5000_0100 to un-lock this bit. Reference the register REGWRPROT at address SYS_BA
+ 0x100
0= Normal
1= Reset CPU

Definition at line 2073 of file NUC029FAE.h.

◆ IPRSTC2

__IO uint32_t SYS_T::IPRSTC2

IPRSTC2

Offset: 0x0C Peripheral Reset Control Resister 2

Bits Field Descriptions
[1] GPIO_RST GPIO (P0~P4) controller Reset
0= GPIO controller normal operation
1= GPIO controller reset
[2] TMR0_RST Timer0 controller Reset
0= Timer0 controller normal operation
1= Timer0 controller reset
[3] TMR1_RST Timer1 controller Reset
0= Timer1 controller normal operation
1= Timer1 controller reset
[8] I2C_RST I2C controller Reset
0= I2C controller normal operation
1= I2C controller reset
[12] SPI_RST SPI controller Reset
0= SPI controller normal operation
1= SPI controller reset
[16] UART_RST UART controller Reset
0= UART controller Normal operation
1= UART controller reset
[20] PWM_RST PWM controller Reset
0= PWM controller normal operation
1= PWM controller reset
[22] ACMP_RST ACMP controller Reset
0= ACMP controller normal operation
1= ACMP controller reset
[28] ADC_RST ADC Controller Reset
0= ADC controller normal operation
1= ADC controller reset

Definition at line 2110 of file NUC029FAE.h.

◆ IRCR

__IO uint32_t UART_T::IRCR

Offset: 0x0028 UART IrDA Control Register

Definition at line 2883 of file NUC029FAE.h.

◆ IRCTRIMCTL

__IO uint32_t SYS_T::IRCTRIMCTL

IRCTRIMCTL

Offset: 0x80 HIRC Trim Control Register

Bits Field Descriptions
[0] TRIM_SEL Trim Frequency Selection
This bit is to enable the HIRC auto trim.
When setting this bit to "1", the HFIRC auto trim function will trim HIRC to 22.1184 MHz
automatically based on the 32.768 KHz reference clock.
During auto trim operation, if 32.768 KHz clock error is detected or trim retry limitation
count reached, this field will be cleared to "0" automatically.
0 = HIRC auto trim function Disabled.
1 = HIRC auto trim function Enabled and HIRC trimmed to 22.1184 MHz.
[5:4] TRIM_LOOP Trim Calculation Loop
This field defines trim value calculation based on the number of 32.768 KHz clock.
This field also defines how many times the auto trim circuit will try to update the
HIRC trim value before the frequency of HIRC is locked.
Once the HIRC is locked, the internal trim value update counter will be reset
If the trim value update counter reaches this limitation value and frequency of HIRC
is still not locked, the auto trim operation will be disabled and TRIM_SEL will be cleared to "0".
00 = Trim value calculation is based on average difference in 4 32.768 KHz clock and trim retry count limitation is 64.
01 = Trim value calculation is based on average difference in 8 32.768 KHz clock and trim retry count limitation is 128.
10 = Trim value calculation is based on average difference in 16 32.768 KHz clock and trim retry count limitation is 256.
11 = Trim value calculation is based on average difference in 32 32.768 KHz clock and trim retry count limitation is 512.

Definition at line 2501 of file NUC029FAE.h.

◆ IRCTRIMIER

__IO uint32_t SYS_T::IRCTRIMIER

IRCTRIMIER

Offset: 0x84 HIRC Trim Interrupt Enable Register

Bits Field Descriptions
[1] TRIM_FAIL_IEN Trim Failure Interrupt Enable
This bit controls if an interrupt will be triggered while HIRC trim value update limitation
count is reached and HIRC frequency is still not locked on target frequency set by TRIM_SEL.
If this bit is high and TRIM_FAIL_INT is set during auto trim operation, an interrupt will be
triggered to notify that HFIRC trim value update limitation count is reached.
0 = TRIM_FAIL_INT status Disabled to trigger an interrupt to CPU.
1 = TRIM_FAIL_INT status Enabled to trigger an interrupt to CPU.
[2] 32K_ERR_IEN 32.768 KHz Clock Error Interrupt Enable
This bit controls if CPU could get an interrupt while 32.768 KHz clock is inaccurate during
auto trim operation.
If this bit is high, and 32K_ERR_INT is set during auto trim operation, an interrupt will be triggered
to notify the 32.768 KHz clock frequency is inaccurate.
0 = 32K_ERR_INT status Disabled to trigger an interrupt to CPU.
1 = 32K_ERR_INT status Enabled to trigger an interrupt to CPU.

Definition at line 2525 of file NUC029FAE.h.

◆ IRCTRIMISR

__IO uint32_t SYS_T::IRCTRIMISR

IRCTRIMISR

Offset: 0x88 HIRC Trim Interrupt Status Register

Bits Field Descriptions
[0] FREQ_LOCK HIRC Frequency Lock Status
1 = This bit indicates the HIRC frequency lock.
[1] TRIM_FAIL_INT Trim Failure Interrupt Status
This bit indicates that HIRC trim value update limitation count reached and HIRC
clock frequency still doesn't lock. Once this bit is set, the auto trim operation
stopped and TRIM_SEL will be cleared to "0" by hardware automatically.
If this bit is set and TRIM_FAIL_IEN is high, an interrupt will be triggered to notify
that HIRC trim value update limitation count was reached. Write "1" to clear this to zero.
0 = Trim value update limitation count is not reached.
1 = Trim value update limitation count is reached and HFIRC frequency is still not locked.
[2] 32K_ERR_INT 32.768 KHz Clock Error Interrupt Status
This bit indicates that 32.768 KHz clock frequency is inaccuracy. Once this bit is set, the
auto trim operation stopped and TRIM_SEL will be cleared to "0" by hardware automatically.
If this bit is set and 32K_ERR_IEN is high, an interrupt will be triggered to notify the
32.768 KHz clock frequency is inaccuracy. Write "1" to clear this to zero.
0 = 32.768 KHz clock frequency is accuracy.
1 = 32.768 KHz clock frequency is inaccuracy.

Definition at line 2552 of file NUC029FAE.h.

◆ IRQSRC

__I uint32_t INT_T::IRQSRC[32]

Offset: 0x0000 ~ 0x007C Interrupt Source Identity Registers

Definition at line 1157 of file NUC029FAE.h.

◆ ISPADR

__IO uint32_t FMC_T::ISPADR

ISPADR

Offset: 0x04 ISP Address Register

Bits Field Descriptions
[31:0] ISPADR ISP Address
NuMicro NUC029FAETM series supports word program only. ISPADR[1:0] must be kept
00b for ISP operation.

Definition at line 817 of file NUC029FAE.h.

◆ ISPCMD

__IO uint32_t FMC_T::ISPCMD

ISPCMD

Offset: 0x0C ISP Command Register

Bits Field Descriptions
[5:0] FOEN_FCEN_FCTRL ISP Command
ISP command table is shown below:
Operation Mode, FOEN, FCEN, FCTRL[3:0]
Read , 0, 0, 0000
Program , 1, 0, 0001
Page Erase , 1, 0, 0010
Read CID , 0, 0, 1011
Read DID , 0, 0, 1100
Read UID , 0, 0, 0100

Definition at line 849 of file NUC029FAE.h.

◆ ISPCON

__IO uint32_t FMC_T::ISPCON

ISPCON

Offset: 0x00 ISP Control Register

Bits Field Descriptions
[0] ISPEN ISP Enable
ISP function enable bit. Set this bit to enable ISP function.
1 = Enable ISP function
0 = Disable ISP function
[1] BS Boot Select
Set/clear this bit to select next booting from LDROM/APROM, respectively.
This bit also functions as MCU booting status flag, which can be used to
check where MCU booted from. This bit is initiated with the inverse value
of CBS in Config0 after power-on reset; It keeps the same value at other reset.
1 = Boot from LDROM
0 = Boot from APROM
[4] CFGUEN Enable Config-bits Update by ISP
1 = Enable ISP can update config-bits
0 = Disable ISP can update config-bits.
[5] LDUEN LDROM Update Enable
LDROM update enable bit.
1 = LDROM can be updated when the MCU runs in APROM.
0 = LDROM cannot be updated
[6] ISPFF ISP Fail Flag
This bit is set by hardware when a triggered ISP meets any of the following conditions:
(1) APROM writes to itself.
(2) LDROM writes to itself.
(3) CONFIG is erased/programmed when the MCU is running in APROM.
(4) Destination address is illegal, such as over an available range.
Write 1 to clear.
[7] SWRST Software Reset
Writing 1 to this bit to start software reset.
It is cleared by hardware after reset is finished.
[10:8] PT Flash Program Time
000 = 40 us
001 = 45 us
010 = 50 us
011 = 55 us
100 = 20 us
101 = 25 us
110 = 30 us
111 = 35 us
[14:12] ET Flash Erase Time
000 = 20 ms (default)
001 = 25 ms
010 = 30 ms
011 = 35 ms
100 = 3 ms
101 = 5 ms
110 = 10 ms
111 = 15 ms

Definition at line 804 of file NUC029FAE.h.

◆ ISPDAT

__IO uint32_t FMC_T::ISPDAT

ISPDAT

Offset: 0x08 ISP Data Register

Bits Field Descriptions
[31:0] ISPDAT ISP Data
Write data to this register before ISP program operation
Read data from this register after ISP read operation

Definition at line 830 of file NUC029FAE.h.

◆ ISPTRG

__IO uint32_t FMC_T::ISPTRG

ISPTRG

Offset: 0x10 ISP Trigger Control Register

Bits Field Descriptions
[0] ISPGO ISP start trigger
Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP
operation is finish.
1 = ISP is on going
0 = ISP operation is finished.

Definition at line 864 of file NUC029FAE.h.

◆ ISR

__IO uint32_t UART_T::ISR

Offset: 0x001C UART Interrupt Status Register

Definition at line 2880 of file NUC029FAE.h.

◆ ISRC

__IO uint32_t GPIO_T::ISRC

Offset: 0x0020 GPIO Port Interrupt Source Flag

Definition at line 938 of file NUC029FAE.h.

◆ LCR

__IO uint32_t UART_T::LCR

Offset: 0x000C UART Line Control Register

Definition at line 2876 of file NUC029FAE.h.

◆ MCR

__IO uint32_t UART_T::MCR

Offset: 0x0010 UART Modem Control Register

Definition at line 2877 of file NUC029FAE.h.

◆ MCUIRQ

__IO uint32_t INT_T::MCUIRQ

Offset: 0x0084 MCU IRQ Number Identity Register

Definition at line 1159 of file NUC029FAE.h.

◆ MSR

__IO uint32_t UART_T::MSR

Offset: 0x0014 UART Modem Status Register

Definition at line 2878 of file NUC029FAE.h.

◆ NMICNO

__IO uint32_t INT_T::NMICNO

Offset: 0x0080 NMI Source Interrupt Select Control Register

Definition at line 1158 of file NUC029FAE.h.

◆ OFFD

__IO uint32_t GPIO_T::OFFD

Offset: 0x0004 GPIO Port Bit Off Digital Enable

Definition at line 931 of file NUC029FAE.h.

◆ P0_MFP

__IO uint32_t SYS_T::P0_MFP

P0_MFP

Offset: 0x30 P0 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] P0_MFP P0 multiple function Selection
The pin function of P0 is depending on P0_MFP and P0_ALT.
Refer to P0_ALT descriptions in detail.
[8] P0_ALT0 P0.0 alternate function Selection
The pin function of P0.0 is depend on P0_MFP[0] and P0_ALT[0].
P0_ALT[0]P0_MFP[0] = P0.0 Function
00 = P0.0
10 = CTS(UART)
11 = TX(UART)
[9] P0_ALT1 P0.1 alternate function Selection
The pin function of P0.1 is depend on P0_MFP[1] and P0_ALT[1].
P0_ALT[1] P0_MFP[1] = P0.1 Function
00 = P0.1
01 = SPISS (SPI)
10 = RTS(UART)
11 = RX(UART)
[12] P0_ALT4 P0.4 alternate function Selection
The pin function of P0.4 is depend on P0_MFP[4] and P0_ALT[4].
P0_ALT[4] P0_MFP[4] = P0.4 Function
00 = P0.4
01 = Reserved
10 = SPISS(SPI)
11 = PWM5(PWM)
[13] P0_ALT5 P0.5 alternate function Selection
The pin function of P0.5 is depend on P0_MFP[5] and P0_ALT[5].
P0_ALT[5] P0_MFP[5] = P0.5 Function
00 = P0.5
01 = Reserved
10 = MOSI(SPI)
11 = Reserved
[14] P0_ALT6 P0.6 alternate function Selection
The pin function of P0.6 is depend on P0_MFP[6] and P0_ALT[6].
P0_ALT[6] P0_MFP[6] = P0.6 Function
00 = P0.6
01 = Reserved
10 = MISO(SPI)
11 = Reserved
[15] P0_ALT7 P0.7 alternate function Selection
The pin function of P0.7 is depend on P0_MFP[7] and P0_ALT[7].
P0_ALT[7] P0_MFP[7] = P0.7 Function
00 = P0.7
01 = Reserved
10 = SPICLK(SPI)
11 = Reserved
[23:16] P0_TYPEn P0[7:0] input Schmitt Trigger function Enable
1= P0[7:0] I/O input Schmitt Trigger function enable
0= P0[7:0] I/O input Schmitt Trigger function disable

Definition at line 2221 of file NUC029FAE.h.

◆ P1_MFP

__IO uint32_t SYS_T::P1_MFP

P1_MFP

Offset: 0x34 P1 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] P1_MFP P1 multiple function Selection
The pin function of P1 is depending on P1_MFP and P1_ALT.
Refer to P1_ALT descriptions in detail.
[8] P1_ALT0 P1.0 alternate function Selection
The pin function of P1.0 is depend on P1_MFP[0] and P1_ALT[0].
P1_ALT[0] P1_MFP[0] = P1.0 Function
00 = P1.0
01 = AIN1(ADC)
10 = Reserved
11 = CPP0 (ACMP)
[10] P1_ALT2 P1.2 alternate function Selection
The pin function of P1.2 is depend on P1_MFP[2] and P1_ALT[2].
P1_ALT[2] P1_MFP[2] = P1.2 Function
00 = P1.2
01 = AIN2(ADC)
10 = RX(UART)
11 = CPP0 (ACMP)
[11] P1_ALT3 P1.3 alternate function Selection
The pin function of P1.3 is depend on P1_MFP[3] and P1_ALT[3].
P1_ALT[3] P1_MFP[3] = P1.3 Function
00 = P1.3
01 = AIN3(ADC)
10 = TX(UART)
11 = CPP0 (ACMP)
[12] P1_ALT4 P1.4 alternate function Selection
The pin function of P1.4 is depend on P1_MFP[4] and P1_ALT[4].
P1_ALT[4] P1_MFP[4] = P1.4 Function
00 = P1.4
01 = AIN4(ADC)
10 = Reserved
11 = CPN0 (CMP)
[13] P1_ALT5 P1.5 alternate function Selection
The pin function of P1.5 is depend on P1_MFP[5] and P1_ALT[5].
P1_ALT[5] P1_MFP[5] = P1.5 Function
00 = P1.5
01 = AIN5(ADC)
10 = Reserved
11 = CPP0 (CMP)
[23:16] P1_TYPEn P1[7:0] input Schmitt Trigger function Enable
1= P1[7:0] I/O input Schmitt Trigger function enable
0= P1[7:0] I/O input Schmitt Trigger function disable

Definition at line 2272 of file NUC029FAE.h.

◆ P2_MFP

__IO uint32_t SYS_T::P2_MFP

P2_MFP

Offset: 0x38 P2 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] P2_MFP P2 multiple function Selection
The pin function of P2 is depending on P2_MFP and P2_ALT.
Refer to P2_ALT descriptions in detail.
[10] P2_ALT2 P2.2 alternate function Selection
The pin function of P2.2 is depend on P2_MFP[2] and P2_ALT[2].
P2_ALT[2] P2_MFP[2] = P2.2 Function
00 = P2.2
01 = Reserved
10 = PWM0(PWM)
11 = Reserved
[11] P2_ALT3 P2.3 alternate function Selection
The pin function of P2.3 is depend on P2_MFP[3] and P2_ALT[3].
P2_ALT[3] P2_MFP[3] = P2.3 Function
00 = P2.3
01 = Reserved
10 = PWM1(PWM)
11 = Reserved
[12] P2_ALT4 P2.4 alternate function Selection
The pin function of P2.4 is depend on P2_MFP[4] and P2_ALT[4].
P2_ALT[4] P2_MFP[4] = P0.4 Function
00 = P2.4
01 = Reserved
10 = PWM2(PWM)
11 = Reserved
[13] P2_ALT5 P2.5 alternate function Selection
The pin function of P2.5 is depend on P2_MFP[5] and P2_ALT[5].
P2_ALT[5] P2_MFP[5] = P2.5 Function
00 = P2.5
01 = Reserved
10 = PWM3(PWM)
11 = Reserved
[14] P2_ALT6 P2.6 alternate function Selection
The pin function of P2.6 is depend on P2_MFP[6] and P2_ALT[6].
P2_ALT[6] P2_MFP[6] = P2.6 Function
00 = P2.6
01 = Reserved
10 = PWM4(PWM)
11 = CPO1
[23:16] P2_TYPEn P2[7:0] input Schmitt Trigger function Enable
1= P2[7:0] I/O input Schmitt Trigger function enable
0= P2[7:0] I/O input Schmitt Trigger function disable

Definition at line 2323 of file NUC029FAE.h.

◆ P3_MFP

__IO uint32_t SYS_T::P3_MFP

P3_MFP

Offset: 0x3C P3 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] P3_MFP P3 multiple function Selection
The pin function of P3 is depending on P3_MFP and P3_ALT.
Refer to P3_ALT descriptions in detail.
[8] P3_ALT0 P3.0 alternate function Selection
The pin function of P3.0 is depend on P3_MFP[0] and P3_ALT[0].
P3_ALT[0] P3_MFP[0] = P3.0 Function
00 = P3.0
01 = Reserved
10 = CPN1
11 = AIN6(ADC)
[9] P3_ALT1 P3.1 alternate function Selection
The pin function of P3.1 is depend on P3_MFP[1] and P3_ALT[1].
P3_ALT[1] P3_MFP[1] = P3.1 Function
00 = P3.1
01 = Reserved
10 = CPP1
11 = AIN7(ADC)
[10] P3_ALT2 P3.2 alternate function Selection
The pin function of P3.2 is depend on P3_MFP[2] and P3_ALT[2].
P3_ALT[2] P3_MFP[2] = P3.2 Function
00 = P3.2
01 = /INT0
10 = T0EX
11 = STADC(ADC)
[12] P3_ALT4 P3.4 alternate function Selection
The pin function of P3.4 is depend on P3_MFP[4] and P3_ALT[4].
P3_ALT[4] P3_MFP[4] = P3.4 Function
00 = P3.4
01 = T0(Timer0)
10 = SDA(I2C)
11 = CPP1(ACMP)
[13] P3_ALT5 P3.5 alternate function Selection
The pin function of P3.5 is depend on P3_MFP[5] and P3_ALT[5].
P3_ALT[5] P3_MFP[5] = P3.5 Function
00 = P3.5
01 = T1(Timer1)
10 = SCL(I2C)
11 = CPP1(ACMP)
[14] P3_ALT6 P3.6 alternate function Selection
The pin function of P3.6 is depend on P3_MFP[6] and P3_ALT[6].
P3_ALT[6] P3_MFP[6] = P3.6 Function
00 = P3.6
01 = T1EX
10 = CKO(Clock Driver output)
11 = CPO0(CMP)
[23:16] P3_TYPEn P3[7:0] input Schmitt Trigger function Enable
1= P3[7:0] I/O input Schmitt Trigger function enable
0= P3[7:0] I/O input Schmitt Trigger function disable
[24] P32CPP1 P3.2 Alternate Function Selection Extension
0 = P3.2 is set by P3_ALT[2] and P3_MFP[2]
1 = P3.2 is set to CPP1 of ACMP1

Definition at line 2384 of file NUC029FAE.h.

◆ P4_MFP

__IO uint32_t SYS_T::P4_MFP

P4_MFP

Offset: 0x40 P4 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] P4_MFP P4 multiple function Selection
The pin function of P4 is depending on P4_MFP and P4_ALT.
Refer to P4_ALT descriptions in detail.
[14] P4_ALT6 P4.6 alternate function Selection
The pin function of P4.6 is depend on P4_MFP[6] and P4_ALT[6].
P4_ALT[6] P4_MFP[6] = P4.6 Function
00 = P4.6
01 = ICE_CLK(ICE)
1x = Reserved
[15] P4_ALT7 P4.7 alternate function Selection
The pin function of P4.7 is depend on P4_MFP[7] and P4_ALT[7].
P4_ALT[7] P4_MFP[7] = P4.7 Function
00 = P4.7
01 = ICE_DAT(ICE)
1x = Reserved
[23:16] P4_TYPEn P4[7:0] input Schmitt Trigger function Enable
1= P4[7:0] I/O input Schmitt Trigger function enable
0= P4[7:0] I/O input Schmitt Trigger function disable

Definition at line 2412 of file NUC029FAE.h.

◆ P5_MFP

__IO uint32_t SYS_T::P5_MFP

P5_MFP

Offset: 0x44 P5 Multiple Function and Input Type Control Register

Bits Field Descriptions
[7:0] P5_MFP P5 multiple function Selection
The pin function of P5 is depending on P5_MFP and P5_ALT.
Refer to P5_ALT descriptions in detail.
[8] P5_ALT0 P5.0 alternate function Selection
The pin function of P5.0 is depend on P5_MFP[0] and P5_ALT[0].
P5_ALT[0] P5_MFP[0] = P5.0 Function
00 = P5.0
01 = XTAL1
1x = Reserved
[9] P5_ALT1 P5.1 alternate function Selection
The pin function of P5.1 is depend on P5_MFP[1] and P5_ALT[1].
P5_ALT[1] P5_MFP[1] = P5.1 Function
00 = P5.1
01 = XTAL2
1x = Reserved
[10] P5_ALT2 P5.2 alternate function Selection
The pin function of P5.2 is depend on P5_MFP[2] and P5_ALT[2].
P5_ALT[2] P5_MFP[2] = P5.2 Function
00 = P5.2
01 = /INT1
1x = Reserved
[11] P5_ALT3 P5.3 alternate function Selection
The pin function of P5.3 is depend on P5_MFP[3] and P5_ALT[3].
P5_ALT[3] P5_MFP[3] = P5.3 Function
00 = P5.3
01 = AIN0(ADC)
1x = Reserved
[12] P5_ALT4 P5.4 alternate function Selection
The pin function of P5.4 is depend on P5_MFP[4] and P5_ALT[4].
P5_ALT[4] P5_MFP[4] = P5.4 Function
00 = P5.4
01 = Reserved
1x = Reserved
[13] P5_ALT5 P5.5 alternate function Selection
The pin function of P5.5 is depend on P5_MFP[5] and P5_ALT[5].
P5_ALT[5] P5_MFP[5] = P5.5 Function
00 = P5.5
01 = Reserved
1x = Reserved
[23:16] P5_TYPEn P5[7:0] input Schmitt Trigger function Enable
1= P5[7:0] I/O input Schmitt Trigger function enable
0= P5[7:0] I/O input Schmitt Trigger function disable

Definition at line 2464 of file NUC029FAE.h.

◆ PCR

__IO uint32_t PWM_T::PCR

Offset: 0x0008 PWM Control Register

Definition at line 1175 of file NUC029FAE.h.

◆ PDID

__I uint32_t SYS_T::PDID

PDID

Offset: 0x00 Part Device Identification Number Register.

Bits Field Descriptions
[31:0] PDID This register reflects device part number code. S/W can read this register to identify which device is
used.

Definition at line 2008 of file NUC029FAE.h.

◆ PDZIR

__IO uint32_t PWM_T::PDZIR

Offset: 0x0064 PWM Dead-zone Interval Register

Definition at line 1183 of file NUC029FAE.h.

◆ PFBCON

__IO uint32_t PWM_T::PFBCON

Offset: 0x0060 PWM Fault Brake Control Register

Definition at line 1182 of file NUC029FAE.h.

◆ PHCHG

__IO uint32_t PWM_T::PHCHG

Offset: 0x0078 PWM Phase Changed Register

Definition at line 1188 of file NUC029FAE.h.

◆ PHCHGMASK

__IO uint32_t PWM_T::PHCHGMASK

Offset: 0x0080 PWM Phase Change MASK Register

Definition at line 1190 of file NUC029FAE.h.

◆ PHCHGNXT

__IO uint32_t PWM_T::PHCHGNXT

Offset: 0x007C PWM Next Phase Change Register

Definition at line 1189 of file NUC029FAE.h.

◆ PIER

__IO uint32_t PWM_T::PIER

Offset: 0x0054 PWM Interrupt Enable Register

Definition at line 1179 of file NUC029FAE.h.

◆ PIIR

__IO uint32_t PWM_T::PIIR

Offset: 0x0058 PWM Interrupt Indication Register

Definition at line 1180 of file NUC029FAE.h.

◆ PIN

__I uint32_t GPIO_T::PIN

Offset: 0x0010 GPIO Port Pin Value

Definition at line 934 of file NUC029FAE.h.

◆ PMD

__IO uint32_t GPIO_T::PMD

Offset: 0x0000 GPIO Port Bit Mode Control

Definition at line 930 of file NUC029FAE.h.

◆ POE

__IO uint32_t PWM_T::POE

Offset: 0x005C PWM Output Enable Register

Definition at line 1181 of file NUC029FAE.h.

◆ PPR

__IO uint32_t PWM_T::PPR

Offset: 0x0000 PWM Pre-scale Register

Definition at line 1173 of file NUC029FAE.h.

◆ PWRCON

__IO uint32_t CLK_T::PWRCON

PWRCON

Offset: 0x00 System Power Down Control Register

Bits Field Descriptions
[1:0] XTLCLK_EN External Crystal Oscillator Control
The default clock source is from internal 22.1184 MHz. These two bits are default set to "00"
and the XTAL1 and XTAL2 pins are GPIO.
00 = XTAL1 and XTAL2 are GPIO, disable both XTL32K & XTAL12M
01 = XTAL12M (HXT) Enabled
10 = XTAL32K (LXT) Enabled
11 = XTAL1 is external clock input pin, XTAL2 is GPIO
Note: To enable external XTAL function, P5_ALT[1:0] and P5_MFP[1:0] bits must also be set in P5_MFP.
[2] OSC22M_EN Internal 22.1184 MHz Oscillator Control
1 = 22.1184 MHz Oscillation enable
0 = 22.1184 MHz Oscillation disable
[3] OSC10K_EN Internal 10KHz Oscillator Control
1 = 10KHz Oscillation enable
0 = 10KHz Oscillation disable
[4] PU_DLY Enable the wake up delay counter.
When the chip wakes up from power down mode, the clock control will delay certain clock
cycles to wait system clock stable.
The delayed clock cycle is 4096 clock cycles when chip work at external crystal (4 ~
24MHz), and 256 clock cycles when chip work at 22.1184 MHz oscillator.
1 = Enable the clock cycle delay
0 = Disable the clock cycle delay
[5] WINT_EN Power down mode wake Up Interrupt Enable
0 = Disable
1 = Enable. The interrupt will occur when Power down mode wakeup.
[6] PD_WU_STS Chip power down wake up status flag
Set by "power down wake up", it indicates that resume from power down mode
The flag is set if the GPIO, UART, WDT, ACMP, Timer or BOD wakeup
Write 1 to clear the bit
Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
[7] PWR_DOWN System Power-down Active or Enable Bit
When chip waked-up from power-down, this bit is automatically cleared, and user needs to set
this bit again for the next power-down.
In Power-down mode, the LDO, external crystal and the 22.1184 MHz OSC will be disabled, and
the 10K enable is not controlled by this bit.
Note: If XTLCLK_EN[1:0] = 10 (enable 32 KHz External Crystal Oscillator) and when PWR_DOWN_EN ="1" (system entering
Power-down mode), the external crystal oscillator cannot be disabled to ensure system wake-up enabled.
When power down, all of the AMBA clocks (HCLKx, CPU clock and the PCLKx) are also disabled, and the clock
source selection is ignored. The IP engine clock is not controlled by this bit if the IP clock source is from
the 10K clock and the WDT from 10K).
1 = Chip entering the Power-down mode instantly or wait CPU Idle command
0 = Chip operated in Normal mode or CPU enters into Idle mode.
[9] PD_32K This bit controls the crystal oscillator active or not in Power-down mode.
1 = If XTLCLK_EN[1:0] = 10, 32.768 KHz crystal oscillator (LXT) is still active in Power-down mode.
0 = No effect to Power-down mode

Definition at line 257 of file NUC029FAE.h.

◆ RBR [1/2]

__I uint32_t UART_T::RBR

Offset: 0x0000 UART Receive Buffer Register

Definition at line 2871 of file NUC029FAE.h.

◆  [2/2]

__I uint32_t { ... } ::RBR

Offset: 0x0000 UART Receive Buffer Register

Definition at line 2871 of file NUC029FAE.h.

◆ RegLockAddr

__IO uint32_t SYS_T::RegLockAddr

RegLockAddr

Offset: 0x100 Register Lock Key Address Register

Bits Field Descriptions
[0] RegUnLock Register Write-Protected Disable index (Read only)
1 = Protected registers are Unlock.
0 = Protected registers are locked. Any write to the target register is ignored.
The Protected registers are:
IPRSTC1 0x5000_0008 None
BODCR 0x5000_0018 None
LDOCR 0x5000_001C None
PORCR 0x5000_0024 None
PWRCON 0x5000_0200 bit[6] is not protected for power, wake-up interrupt clear
APBCLK bit[0] 0x5000_0208 bit[0] is watch dog clock enable
CLKSEL0 0x5000_0210 HCLK and CPU STCLK clock source select
CLK_SEL1 bit[1:0] 0x5000_0214 Watch dog clock source select
ISPCON 0x5000_C000 Flash ISP Control register
WTCR 0x4000_4000 None
NMI_SEL[8] - address 0x5000_380 (NMI interrupt source enable)

Definition at line 2585 of file NUC029FAE.h.

◆ RESERVED0 [1/6]

uint32_t CLK_T::RESERVED0

Reserved

Definition at line 455 of file NUC029FAE.h.

◆ RESERVED0 [2/6]

uint32_t SYS_T::RESERVED0[2]

RESERVED0


Definition at line 2118 of file NUC029FAE.h.

◆ RESERVED0 [3/6]

uint32_t PWM_T::RESERVED0[6]

Offset: 0x003C ~ 0x0050 Reserved

Definition at line 1178 of file NUC029FAE.h.

◆ RESERVED0 [4/6]

uint32_t ADC_T::RESERVED0[7]

Offset: 0x0004 ~ 0x001C Reserved

Definition at line 645 of file NUC029FAE.h.

◆ RESERVED0 [5/6]

uint32_t I2C_T::RESERVED0

Offset: 0x0034 Reserved

Definition at line 1055 of file NUC029FAE.h.

◆ RESERVED0 [6/6]

uint32_t SPI_T::RESERVED0

Offset: 0x000C Reserved

Definition at line 1826 of file NUC029FAE.h.

◆ RESERVED1 [1/3]

uint32_t I2C_T::RESERVED1

Offset: 0x0038 Reserved

Definition at line 1056 of file NUC029FAE.h.

◆ RESERVED1 [2/3]

uint32_t SPI_T::RESERVED1[3]

Offset: 0x0014~0x001C Reserved

Definition at line 1828 of file NUC029FAE.h.

◆ RESERVED1 [3/3]

uint32_t SYS_T::RESERVED1[5]

RESERVED1


Definition at line 2164 of file NUC029FAE.h.

◆ RESERVED2

uint32_t SPI_T::RESERVED2[6]

Offset: 0x0024 ~ 0x0038 Reserved

Definition at line 1830 of file NUC029FAE.h.

◆ RESERVED3

uint32_t SYS_T::RESERVED3[14]

RESERVED3


Definition at line 2472 of file NUC029FAE.h.

◆ RESERVED4

uint32_t SYS_T::RESERVED4[29]

RESERVED4


Definition at line 2560 of file NUC029FAE.h.

◆ RSTSRC

__IO uint32_t SYS_T::RSTSRC

RSTSRC

Offset: 0x04 System Reset Source Register

Bits Field Descriptions
[31:8] Reserved Reserved
[7] RSTS_CPU The RSTS_CPU flag is set by hardware if software writes CPU_RST (IPRSTC1[1]) 1 to reset Cortex-M0 CPU kernel and Flash memory controller (FMC).
1 = The Cortex-M0 CPU kernel and FMC are reset by software setting CPU_RST to 1.
0 = No reset from CPU
Software can write 1 to clear this bit to zero.
[6] Reserved Reserved
[5] RSTS_MCU The RSTS_MCU flag is set by the "reset signal" from the MCU Cortex_M0 kernel to indicate the previous reset source.
1= The MCU Cortex_M0 had issued the reset signal to reset the system by software writing 1 to bit SYSRESTREQ(AIRCR[2], Application Interrupt and Reset Control Register) in system control registers of Cortex_M0 kernel.
0= No reset from MCU
This bit is cleared by writing 1 to itself.
[4] RSTS_BOD The RSTS_BOD flag is set by the "reset signal" from the Brown-Out Detector to indicate the previous reset source.
1= The Brown-Out Detector module had issued the reset signal to reset the system.
0= No reset from BOD
Software can write 1 to clear this bit to zero.
[3] Reserved Reserved
[2] RSTS_WDT The RSTS_WDT flag is set by the "reset signal" from the Watchdog timer to indicate the previous reset source.
1= The Watchdog timer had issued the reset signal to reset the system.
0= No reset from Watchdog timer
Software can write 1 to clear this bit to zero.
[1] RSTS_RESET The RSTS_RESET flag is set by the "reset signal" from the /RESET pin to indicate the previous reset source.
1= The Pin /RESET had issued the reset signal to reset the system.
0= No reset from Pin /RESET
Software can write 1 to clear this bit to zero.
[0] RSTS_POR The RSTS_POR flag is set by the "reset signal", which is from the Power-On Reset (POR) module or bit CHIP_RST (IPRSTC1[0]) is set, to indicate the previous reset source.
1= The Power-On-Reset (POR) or CHIP_RST had issued the reset signal to reset the system.
0= No reset from POR or CHIP_RST
Software can write 1 to clear this bit to zero.

Definition at line 2045 of file NUC029FAE.h.

◆ RX

__I uint32_t SPI_T::RX

Offset: 0x0010 SPI Data Receive Register

Definition at line 1827 of file NUC029FAE.h.

◆ SSR

__IO uint32_t SPI_T::SSR

Offset: 0x0008 SPI Slave Select Register

Definition at line 1825 of file NUC029FAE.h.

◆ STATUS

__IO uint32_t SPI_T::STATUS

Offset: 0x0044 SPI Status Register

Definition at line 1833 of file NUC029FAE.h.

◆ TCAP

__I uint32_t TIMER_T::TCAP

Offset: 0x0010 Timer Capture Data Register

Definition at line 2765 of file NUC029FAE.h.

◆ TCMPR

__IO uint32_t TIMER_T::TCMPR

Offset: 0x0004 Timer Compare Register

Definition at line 2762 of file NUC029FAE.h.

◆ TCSR

__IO uint32_t TIMER_T::TCSR

Offset: 0x0000 Timer Control and Status Register

Definition at line 2761 of file NUC029FAE.h.

◆ TDR

__I uint32_t TIMER_T::TDR

Offset: 0x000C Timer Data Register

Definition at line 2764 of file NUC029FAE.h.

◆ TEXCON

__IO uint32_t TIMER_T::TEXCON

Offset: 0x0014 Timer External Control Register

Definition at line 2766 of file NUC029FAE.h.

◆ TEXISR

__IO uint32_t TIMER_T::TEXISR

Offset: 0x0018 Timer External Interrupt Status Register

Definition at line 2767 of file NUC029FAE.h.

◆ THR [1/2]

__O uint32_t UART_T::THR

Offset: 0x0000 UART Transmit Holding Register

Definition at line 2872 of file NUC029FAE.h.

◆  [2/2]

__O uint32_t { ... } ::THR

Offset: 0x0000 UART Transmit Holding Register

Definition at line 2872 of file NUC029FAE.h.

◆ TISR

__IO uint32_t TIMER_T::TISR

Offset: 0x0008 Timer Interrupt Status Register

Definition at line 2763 of file NUC029FAE.h.

◆ TOR

__IO uint32_t UART_T::TOR

Offset: 0x0020 UART Time-out Register

Definition at line 2881 of file NUC029FAE.h.

◆ TRGCON0

__IO uint32_t PWM_T::TRGCON0

Offset: 0x0068 PWM Trigger Control Register 0

Definition at line 1184 of file NUC029FAE.h.

◆ TRGCON1

__IO uint32_t PWM_T::TRGCON1

Offset: 0x006C PWM Trigger Control Register 1

Definition at line 1185 of file NUC029FAE.h.

◆ TRGSTS0

__IO uint32_t PWM_T::TRGSTS0

Offset: 0x0070 PWM Trigger Status Register 0

Definition at line 1186 of file NUC029FAE.h.

◆ TRGSTS1

__IO uint32_t PWM_T::TRGSTS1

Offset: 0x0074 PWM Trigger Status Register 1

Definition at line 1187 of file NUC029FAE.h.

◆ TX

__O uint32_t SPI_T::TX

Offset: 0x0020 SPI Data Transmit Register

Definition at line 1829 of file NUC029FAE.h.

◆ WTCR

__IO uint32_t WDT_T::WTCR

Offset: 0x0000 Watchdog Timer Control Register

Definition at line 3126 of file NUC029FAE.h.