NUC029FAE_BSP V3.01.004
The Board Support Package for NUC029FAE MCU
Variables

Functions that configure the System. More...

Collaboration diagram for SysTick Functions:

Variables

uint32_t   APSR_Type::_reserved0:28
 
uint32_t   APSR_Type::V:1
 
uint32_t   APSR_Type::C:1
 
uint32_t   APSR_Type::Z:1
 
uint32_t   APSR_Type::N:1
 
struct {
   uint32_t   APSR_Type::_reserved0:28
 
   uint32_t   APSR_Type::V:1
 
   uint32_t   APSR_Type::C:1
 
   uint32_t   APSR_Type::Z:1
 
   uint32_t   APSR_Type::N:1
 
APSR_Type::b
 
uint32_t APSR_Type::w
 
uint32_t   IPSR_Type::ISR:9
 
uint32_t   IPSR_Type::_reserved0:23
 
struct {
   uint32_t   IPSR_Type::ISR:9
 
   uint32_t   IPSR_Type::_reserved0:23
 
IPSR_Type::b
 
uint32_t IPSR_Type::w
 
uint32_t   xPSR_Type::ISR:9
 
uint32_t   xPSR_Type::_reserved0:15
 
uint32_t   xPSR_Type::T:1
 
uint32_t   xPSR_Type::_reserved1:3
 
uint32_t   xPSR_Type::V:1
 
uint32_t   xPSR_Type::C:1
 
uint32_t   xPSR_Type::Z:1
 
uint32_t   xPSR_Type::N:1
 
struct {
   uint32_t   xPSR_Type::ISR:9
 
   uint32_t   xPSR_Type::_reserved0:15
 
   uint32_t   xPSR_Type::T:1
 
   uint32_t   xPSR_Type::_reserved1:3
 
   uint32_t   xPSR_Type::V:1
 
   uint32_t   xPSR_Type::C:1
 
   uint32_t   xPSR_Type::Z:1
 
   uint32_t   xPSR_Type::N:1
 
xPSR_Type::b
 
uint32_t xPSR_Type::w
 
uint32_t   CONTROL_Type::_reserved0:1
 
uint32_t   CONTROL_Type::SPSEL:1
 
uint32_t   CONTROL_Type::_reserved1:30
 
struct {
   uint32_t   CONTROL_Type::_reserved0:1
 
   uint32_t   CONTROL_Type::SPSEL:1
 
   uint32_t   CONTROL_Type::_reserved1:30
 
CONTROL_Type::b
 
uint32_t CONTROL_Type::w
 
__IOM uint32_t NVIC_Type::ISER [1U]
 
uint32_t NVIC_Type::RESERVED0 [31U]
 
__IOM uint32_t NVIC_Type::ICER [1U]
 
uint32_t NVIC_Type::RSERVED1 [31U]
 
__IOM uint32_t NVIC_Type::ISPR [1U]
 
uint32_t NVIC_Type::RESERVED2 [31U]
 
__IOM uint32_t NVIC_Type::ICPR [1U]
 
uint32_t NVIC_Type::RESERVED3 [31U]
 
uint32_t NVIC_Type::RESERVED4 [64U]
 
__IOM uint32_t NVIC_Type::IP [8U]
 
__IM uint32_t SCB_Type::CPUID
 
__IOM uint32_t SCB_Type::ICSR
 
uint32_t SCB_Type::RESERVED0
 
__IOM uint32_t SCB_Type::AIRCR
 
__IOM uint32_t SCB_Type::SCR
 
__IOM uint32_t SCB_Type::CCR
 
uint32_t SCB_Type::RESERVED1
 
__IOM uint32_t SCB_Type::SHP [2U]
 
__IOM uint32_t SCB_Type::SHCSR
 
__IOM uint32_t SysTick_Type::CTRL
 
__IOM uint32_t SysTick_Type::LOAD
 
__IOM uint32_t SysTick_Type::VAL
 
__IM uint32_t SysTick_Type::CALIB
 
__STATIC_INLINE uint32_t SysTick_Config (uint32_t ticks)
 System Tick Configuration. More...
 

Detailed Description

Functions that configure the System.

Function Documentation

◆ SysTick_Config()

__STATIC_INLINE uint32_t SysTick_Config ( uint32_t  ticks)

System Tick Configuration.

Initializes the System Timer and its interrupt, and starts the System Tick Timer. Counter is in free running mode to generate periodic interrupts.

Parameters
[in]ticksNumber of ticks between two interrupts.
Returns
0 Function succeeded.
1 Function failed.
Note
When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function.

Definition at line 769 of file core_cm0.h.

Here is the call graph for this function:

Variable Documentation

◆ _reserved0 [1/8]

uint32_t APSR_Type::_reserved0

bit: 0..27 Reserved

Definition at line 251 of file core_cm0.h.

◆  [2/8]

uint32_t { ... } ::_reserved0

bit: 0..27 Reserved

Definition at line 251 of file core_cm0.h.

◆ _reserved0 [3/8]

uint32_t IPSR_Type::_reserved0

bit: 9..31 Reserved

Definition at line 282 of file core_cm0.h.

◆  [4/8]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 282 of file core_cm0.h.

◆ _reserved0 [5/8]

uint32_t xPSR_Type::_reserved0

bit: 9..23 Reserved

Definition at line 300 of file core_cm0.h.

◆  [6/8]

uint32_t { ... } ::_reserved0

bit: 9..23 Reserved

Definition at line 300 of file core_cm0.h.

◆  [7/8]

uint32_t { ... } ::_reserved0

bit: 0 Reserved

Definition at line 338 of file core_cm0.h.

◆ _reserved0 [8/8]

uint32_t CONTROL_Type::_reserved0

bit: 0 Reserved

Definition at line 338 of file core_cm0.h.

◆ _reserved1 [1/4]

uint32_t xPSR_Type::_reserved1

bit: 25..27 Reserved

Definition at line 302 of file core_cm0.h.

◆  [2/4]

uint32_t { ... } ::_reserved1

bit: 25..27 Reserved

Definition at line 302 of file core_cm0.h.

◆ _reserved1 [3/4]

uint32_t CONTROL_Type::_reserved1

bit: 2..31 Reserved

Definition at line 340 of file core_cm0.h.

◆  [4/4]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 340 of file core_cm0.h.

◆ AIRCR

__IOM uint32_t SCB_Type::AIRCR

Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

Definition at line 394 of file core_cm0.h.

◆  [1/4]

struct { ... } APSR_Type::b

Structure used for bit access

◆  [2/4]

struct { ... } IPSR_Type::b

Structure used for bit access

◆  [3/4]

struct { ... } xPSR_Type::b

Structure used for bit access

◆  [4/4]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ C [1/4]

uint32_t APSR_Type::C

bit: 29 Carry condition code flag

Definition at line 253 of file core_cm0.h.

◆  [2/4]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 253 of file core_cm0.h.

◆  [3/4]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 304 of file core_cm0.h.

◆ C [4/4]

uint32_t xPSR_Type::C

bit: 29 Carry condition code flag

Definition at line 304 of file core_cm0.h.

◆ CALIB

__IM uint32_t SysTick_Type::CALIB

Offset: 0x00C (R/ ) SysTick Calibration Register

Definition at line 501 of file core_cm0.h.

◆ CCR

__IOM uint32_t SCB_Type::CCR

Offset: 0x014 (R/W) Configuration Control Register

Definition at line 396 of file core_cm0.h.

◆ CPUID

__IM uint32_t SCB_Type::CPUID

Offset: 0x000 (R/ ) CPUID Base Register

Definition at line 391 of file core_cm0.h.

◆ CTRL

__IOM uint32_t SysTick_Type::CTRL

Offset: 0x000 (R/W) SysTick Control and Status Register

Definition at line 498 of file core_cm0.h.

◆ ICER

__IOM uint32_t NVIC_Type::ICER[1U]

Offset: 0x080 (R/W) Interrupt Clear Enable Register

Definition at line 366 of file core_cm0.h.

◆ ICPR

__IOM uint32_t NVIC_Type::ICPR[1U]

Offset: 0x180 (R/W) Interrupt Clear Pending Register

Definition at line 370 of file core_cm0.h.

◆ ICSR

__IOM uint32_t SCB_Type::ICSR

Offset: 0x004 (R/W) Interrupt Control and State Register

Definition at line 392 of file core_cm0.h.

◆ IP

__IOM uint32_t NVIC_Type::IP[8U]

Offset: 0x300 (R/W) Interrupt Priority Register

Definition at line 373 of file core_cm0.h.

◆ ISER

__IOM uint32_t NVIC_Type::ISER[1U]

Offset: 0x000 (R/W) Interrupt Set Enable Register

Definition at line 364 of file core_cm0.h.

◆ ISPR

__IOM uint32_t NVIC_Type::ISPR[1U]

Offset: 0x100 (R/W) Interrupt Set Pending Register

Definition at line 368 of file core_cm0.h.

◆ ISR [1/4]

uint32_t IPSR_Type::ISR

bit: 0.. 8 Exception number

Definition at line 281 of file core_cm0.h.

◆  [2/4]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 281 of file core_cm0.h.

◆ ISR [3/4]

uint32_t xPSR_Type::ISR

bit: 0.. 8 Exception number

Definition at line 299 of file core_cm0.h.

◆  [4/4]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 299 of file core_cm0.h.

◆ LOAD

__IOM uint32_t SysTick_Type::LOAD

Offset: 0x004 (R/W) SysTick Reload Value Register

Definition at line 499 of file core_cm0.h.

◆  [1/4]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 255 of file core_cm0.h.

◆ N [2/4]

uint32_t APSR_Type::N

bit: 31 Negative condition code flag

Definition at line 255 of file core_cm0.h.

◆  [3/4]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 306 of file core_cm0.h.

◆ N [4/4]

uint32_t xPSR_Type::N

bit: 31 Negative condition code flag

Definition at line 306 of file core_cm0.h.

◆ RESERVED0 [1/2]

uint32_t NVIC_Type::RESERVED0[31U]

Definition at line 365 of file core_cm0.h.

◆ RESERVED0 [2/2]

uint32_t SCB_Type::RESERVED0

Definition at line 393 of file core_cm0.h.

◆ RESERVED1

uint32_t SCB_Type::RESERVED1

Definition at line 397 of file core_cm0.h.

◆ RESERVED2

uint32_t NVIC_Type::RESERVED2[31U]

Definition at line 369 of file core_cm0.h.

◆ RESERVED3

uint32_t NVIC_Type::RESERVED3[31U]

Definition at line 371 of file core_cm0.h.

◆ RESERVED4

uint32_t NVIC_Type::RESERVED4[64U]

Definition at line 372 of file core_cm0.h.

◆ RSERVED1

uint32_t NVIC_Type::RSERVED1[31U]

Definition at line 367 of file core_cm0.h.

◆ SCR

__IOM uint32_t SCB_Type::SCR

Offset: 0x010 (R/W) System Control Register

Definition at line 395 of file core_cm0.h.

◆ SHCSR

__IOM uint32_t SCB_Type::SHCSR

Offset: 0x024 (R/W) System Handler Control and State Register

Definition at line 399 of file core_cm0.h.

◆ SHP

__IOM uint32_t SCB_Type::SHP[2U]

Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED

Definition at line 398 of file core_cm0.h.

◆  [1/2]

uint32_t { ... } ::SPSEL

bit: 1 Stack to be used

Definition at line 339 of file core_cm0.h.

◆ SPSEL [2/2]

uint32_t CONTROL_Type::SPSEL

bit: 1 Stack to be used

Definition at line 339 of file core_cm0.h.

◆  [1/2]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 301 of file core_cm0.h.

◆ T [2/2]

uint32_t xPSR_Type::T

bit: 24 Thumb bit (read 0)

Definition at line 301 of file core_cm0.h.

◆ V [1/4]

uint32_t APSR_Type::V

bit: 28 Overflow condition code flag

Definition at line 252 of file core_cm0.h.

◆  [2/4]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 252 of file core_cm0.h.

◆  [3/4]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 303 of file core_cm0.h.

◆ V [4/4]

uint32_t xPSR_Type::V

bit: 28 Overflow condition code flag

Definition at line 303 of file core_cm0.h.

◆ VAL

__IOM uint32_t SysTick_Type::VAL

Offset: 0x008 (R/W) SysTick Current Value Register

Definition at line 500 of file core_cm0.h.

◆ w [1/4]

uint32_t APSR_Type::w

Type used for word access

Definition at line 257 of file core_cm0.h.

◆ w [2/4]

uint32_t IPSR_Type::w

Type used for word access

Definition at line 284 of file core_cm0.h.

◆ w [3/4]

uint32_t xPSR_Type::w

Type used for word access

Definition at line 308 of file core_cm0.h.

◆ w [4/4]

uint32_t CONTROL_Type::w

Type used for word access

Definition at line 342 of file core_cm0.h.

◆  [1/4]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 254 of file core_cm0.h.

◆ Z [2/4]

uint32_t APSR_Type::Z

bit: 30 Zero condition code flag

Definition at line 254 of file core_cm0.h.

◆  [3/4]

uint32_t { ... } ::Z

bit: 30 Zero condition code flag

Definition at line 305 of file core_cm0.h.

◆ Z [4/4]

uint32_t xPSR_Type::Z

bit: 30 Zero condition code flag

Definition at line 305 of file core_cm0.h.