Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
adc.c
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1 /**************************************************************************/
12 #include "Nano1X2Series.h"
13 
41 void ADC_Open(ADC_T *adc,
42  uint32_t u32InputMode,
43  uint32_t u32OpMode,
44  uint32_t u32ChMask)
45 {
46 
47  ADC->CR = (ADC->CR & ~ADC_CR_DIFF_Msk) | u32InputMode;
48  ADC->CR = (ADC->CR & ~ADC_CR_ADMD_Msk) | u32OpMode;
49  ADC->CR = (ADC->CR & ~ADC_CR_REFSEL_Msk);
50  ADC->CHEN = u32ChMask;
51  return;
52 }
53 
59 void ADC_Close(ADC_T *adc)
60 {
61  SYS->IPRST_CTL2 |= SYS_IPRST_CTL2_ADC_RST_Msk;
62  SYS->IPRST_CTL2 &= ~SYS_IPRST_CTL2_ADC_RST_Msk;
63  return;
64 
65 }
66 
82  uint32_t u32Source,
83  uint32_t u32Param)
84 {
86  if(u32Source == ADC_TRIGGER_BY_EXT_PIN)
87  {
88  ADC->CR |= u32Source | u32Param | ADC_CR_TRGE_Msk;
89  }
90  else
91  {
92  ADC->CR |= u32Source | ADC_CR_TRGE_Msk;
93  }
94 
95  return;
96 }
97 
104 {
106  return;
107 }
108 
117  uint32_t u32Source,
118  uint32_t u32PDMACnt)
119 {
121  ADC->CR |= (u32PDMACnt << ADC_CR_TMPDMACNT_Pos) | (u32Source << ADC_CR_TMSEL_Pos) | ADC_CR_TMTRGMOD_Msk;
122 
123  return;
124 }
125 
132 {
133  ADC->CR &= ~ADC_CR_TMTRGMOD_Msk;
134 
135  return;
136 }
137 
146  uint32_t u32ChNum,
147  uint32_t u32SampleTime)
148 {
149 
150  if (u32ChNum < 8)
151  ADC->SMPLCNT0 = (ADC->SMPLCNT0 & ~(ADC_SMPLCNT0_CH0SAMPCNT_Msk << (u32ChNum * 4))) | (u32SampleTime << (u32ChNum * 4));
152  else
153  ADC->SMPLCNT1 = (ADC->SMPLCNT1 & ~ADC_SMPLCNT1_INTCHSAMPCNT_Msk) | (u32SampleTime << ADC_SMPLCNT1_INTCHSAMPCNT_Pos);
154 }
155 
167 void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
168 {
169  if(u32Mask & ADC_ADF_INT)
170  ADC->CR |= ADC_CR_ADIE_Msk;
171  if(u32Mask & ADC_CMP0_INT)
172  ADC->CMPR0 |= ADC_CMPR_CMPIE_Msk;
173  if(u32Mask & ADC_CMP1_INT)
174  ADC->CMPR1 |= ADC_CMPR_CMPIE_Msk;
175 
176  return;
177 }
178 
190 void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
191 {
192  if(u32Mask & ADC_ADF_INT)
193  ADC->CR &= ~ADC_CR_ADIE_Msk;
194  if(u32Mask & ADC_CMP0_INT)
195  ADC->CMPR0 &= ~ADC_CMPR_CMPIE_Msk;
196  if(u32Mask & ADC_CMP1_INT)
197  ADC->CMPR1 &= ~ADC_CMPR_CMPIE_Msk;
198 
199  return;
200 }
201 
202 
203  /* end of group NANO1X2_ADC_EXPORTED_FUNCTIONS */
205  /* end of group NANO1X2_ADC_Driver */
207  /* end of group NANO1X2_Device_Driver */
209 
210 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
void ADC_EnableHWTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32Param)
Configure the hardware trigger condition and enable hardware trigger.
Definition: adc.c:81
void ADC_EnableTimerTrigger(ADC_T *adc, uint32_t u32Source, uint32_t u32PDMACnt)
Config and enable timer trigger.
Definition: adc.c:116
#define SYS_IPRST_CTL2_ADC_RST_Msk
#define ADC_CR_TMTRGMOD_Msk
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
Enable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:167
#define ADC_CR_TRGS_Msk
#define ADC_CR_TMPDMACNT_Msk
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
Disable the interrupt(s) selected by u32Mask parameter.
Definition: adc.c:190
#define ADC_TRIGGER_BY_EXT_PIN
Definition: adc.h:49
#define ADC_SMPLCNT1_INTCHSAMPCNT_Msk
void ADC_Close(ADC_T *adc)
Disable ADC module.
Definition: adc.c:59
void ADC_Open(ADC_T *adc, uint32_t u32InputMode, uint32_t u32OpMode, uint32_t u32ChMask)
This API configures ADC module to be ready for convert the input from selected channel.
Definition: adc.c:41
#define ADC_CMP0_INT
Definition: adc.h:56
#define ADC_CR_TMSEL_Pos
Nano102/112 peripheral access layer header file. This file contains all the peripheral register's def...
#define ADC_CR_ADMD_Msk
void ADC_DisableTimerTrigger(ADC_T *adc)
Disable timer trigger ADC function.
Definition: adc.c:131
#define ADC_CR_DIFF_Msk
#define ADC_SMPLCNT1_INTCHSAMPCNT_Pos
#define ADC_ADF_INT
Definition: adc.h:55
#define ADC_SMPLCNT0_CH0SAMPCNT_Msk
void ADC_DisableHWTrigger(ADC_T *adc)
Disable hardware trigger ADC function.
Definition: adc.c:103
#define ADC_CR_TRGCOND_Msk
#define ADC
Pointer to ADC register structure.
#define ADC_CR_TMPDMACNT_Pos
#define ADC_CR_ADIE_Msk
#define ADC_CMP1_INT
Definition: adc.h:57
#define ADC_CR_TRGE_Msk
#define SYS
Pointer to SYS register structure.
#define ADC_CR_TMSEL_Msk
#define ADC_CR_REFSEL_Msk
#define ADC_CMPR_CMPIE_Msk
void ADC_SetExtraSampleTime(ADC_T *adc, uint32_t u32ChNum, uint32_t u32SampleTime)
Configure the hardware trigger condition and enable hardware trigger.
Definition: adc.c:145