40 PDMAGCR->GCRCSR |= (u32Mask << 8);
72 pdma->
CSR = (pdma->
CSR & ~PDMA_CSR_APB_TWS_Msk) | u32Width;
76 pdma->
BCR = (u32TransCount << 2);
80 pdma->
BCR = u32TransCount;
84 pdma->
BCR = (u32TransCount << 1);
105void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
110 pdma->
SAR = u32SrcAddr;
111 pdma->
DAR = u32DstAddr;
148 PDMAGCR->DSSR1 = (
PDMAGCR->DSSR1 & ~DMA_GCR_DSSR1_CH4_SEL_Msk) | u32Peripheral;
154 pdma->
CSR &= ~PDMA_CSR_MODE_SEL_Msk;
155 else if (u32Peripheral & 0x10)
156 pdma->
CSR = (pdma->
CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x4;
158 pdma->
CSR = (pdma->
CSR & ~PDMA_CSR_MODE_SEL_Msk) | 0x8;
177 pdma->
TCR = (pdma->
TCR & ~PDMA_TCR_PDMA_TCR_Msk) | u32TimeOutCnt;
214 pdma->
IER |= u32Mask;
232 pdma->
IER &= ~u32Mask;
Nano102/112 peripheral access layer header file. This file contains all the peripheral register's def...
#define DMA_GCR_DSSR0_CH1_SEL_Pos
#define PDMA_CSR_TRIG_EN_Msk
#define DMA_GCR_DSSR0_CH3_SEL_Pos
#define PDMA_CSR_TO_EN_Pos
#define PDMA_CSR_PDMACEN_Msk
#define PDMA_CSR_SAD_SEL_Msk
#define PDMA_CSR_DAD_SEL_Msk
#define DMA_GCR_DSSR0_CH2_SEL_Pos
void PDMA_SetTransferAddr(uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
Set PDMA Transfer Address.
void PDMA_Trigger(uint32_t u32Ch)
Trigger PDMA.
void PDMA_SetTimeOut(uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
Set PDMA Timeout.
void PDMA_EnableInt(uint32_t u32Ch, uint32_t u32Mask)
Enable Interrupt.
void PDMA_Open(uint32_t u32Mask)
PDMA Open.
void PDMA_Close(void)
PDMA Close.
void PDMA_DisableInt(uint32_t u32Ch, uint32_t u32Mask)
Disable Interrupt.
void PDMA_SetTransferMode(uint32_t u32Ch, uint32_t u32Periphral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
Set PDMA Transfer Mode.
void PDMA_SetTransferCnt(uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
Set PDMA Transfer Count.
#define PDMAGCR
Pointer to PDMA global control register structure.
#define PDMA0_BASE
PDMA0 register base address.