43 CLK->APBCLK &= (~CLK_APBCLK_FDIV0_EN_Msk);
53 CLK->APBCLK &= (~CLK_APBCLK_FDIV1_EN_Msk);
74void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
96void CLK_EnableCKO0(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
99 CLK->CLKSEL2 = (
CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV0_S_Msk)) | u32ClkSrc;
126void CLK_EnableCKO1(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
129 CLK->CLKSEL2 = (
CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV1_S_Msk)) | u32ClkSrc;
145 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
205 uint32_t Div[]= {1,2,4,8,16,1,1,1};
230 uint32_t u32Freq =0, u32PLLSrc;
231 uint32_t u32SRC_N,u32PLL_M,u32PllReg;
233 u32PllReg =
CLK->PLLCTL;
251 u32Freq = u32PLLSrc * u32PLL_M / (u32SRC_N+1);
290 CLK->CLKDIV0 = (
CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLK_N_Msk) | u32ClkDiv;
291 CLK->CLKSEL0 = (
CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_S_Msk) | u32ClkSrc;
385 uint32_t u32tmp=0,u32sel=0,u32div=0;
390 u32tmp = *(
volatile uint32_t *)(u32div);
392 *(
volatile uint32_t *)(u32div) = u32tmp;
398 u32tmp = *(
volatile uint32_t *)(u32sel);
400 *(
volatile uint32_t *)(u32sel) = u32tmp;
415 CLK->PWRCTL |= u32ClkMask;
429 CLK->PWRCTL &= ~u32ClkMask;
518 uint32_t u32PllCr,u32PLL_N,u32PLL_M,u32PLLReg;
527 CLK->PLLCTL &= ~CLK_PLLCTL_PLL_SRC_HIRC;
541 u32PLL_N=u32PllCr/1000000;
542 u32PLL_M=u32PllFreq/1000000;
545 if(u32PLL_M<=32 && u32PLL_N<=16 )
break;
555 CLK->PLLCTL = (
CLK->PLLCTL & ~CLK_PLLCTL_PLL_SRC_HIRC);
557 CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
585 SysTick->VAL = (0x00);
586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
589 while (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0) &&
591 if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0)
611 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
614 SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
616 SysTick->LOAD = u32Count;
618 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
647 int32_t i32TimeOutCnt=2160000;
649 while((
CLK->CLKSTATUS & u32ClkMask) != u32ClkMask)
651 if(i32TimeOutCnt-- <= 0)
Nano102/112 peripheral access layer header file. This file contains all the peripheral register's def...
#define CLK_CLKSEL0_STCLKSEL_HCLK
#define CLK_PLLCTL_PLL_SRC_HXT
#define CLK_PWRCTL_HXT_EN
#define MODULE_CLKSEL_Msk(x)
#define CLK_PLLCTL_PLL_SRC_HIRC
#define MODULE_CLKSEL_Pos(x)
#define CLK_HCLK_CLK_DIVIDER(x)
#define CLK_CLKSEL0_HCLK_S_PLL
#define MODULE_CLKDIV_Pos(x)
#define MODULE_IP_EN_Pos(x)
#define MODULE_CLKDIV_Msk(x)
#define CLK_PWRCTL_LXT_EN
void CLK_DisableCKO1(void)
This function disable frequency output function(1).
void CLK_Idle(void)
This function let system enter to Idle mode.
uint32_t CLK_GetPCLKFreq(void)
This function get PCLK frequency. The frequency unit is Hz.
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
This function set PLL frequency.
void CLK_DisableCKO(void)
This function disable frequency output function.
void CLK_EnableCKO1(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisableCKO0(void)
This function disable frequency output function.
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
void CLK_PowerDown(void)
This function let system enter to Power-down mode.
void CLK_EnableCKO0(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
void CLK_DisablePLL(void)
This function disable PLL.
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
int32_t CLK_SysTickDelay(uint32_t us)
This function execute delay function.
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
void CLK_DisableSysTick(void)
Disable System Tick counter.
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz.
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
#define CLK_PLLCTL_PLL_MLP_Msk
#define CLK_PLLCTL_PLL_SRC_N_Msk
#define CLK_PWRCTL_WK_DLY_Msk
#define CLK_PLLCTL_PLL_SRC_N_Pos
#define CLK_FRQDIV0_DIV1_Pos
#define CLK_CLKSTATUS_PLL_STB_Msk
#define CLK_PLLCTL_PD_Msk
#define CLK_APBCLK_FDIV1_EN_Msk
#define CLK_FRQDIV1_DIV1_Pos
#define CLK_FRQDIV0_FDIV_EN_Msk
#define CLK_APB_DIV_APBDIV_Msk
#define CLK_PLLCTL_PLL_MLP_Pos
#define CLK_PWRCTL_HIRC_FSEL_Msk
#define CLK_PWRCTL_PD_EN_Msk
#define CLK_FRQDIV1_FDIV_EN_Msk
#define CLK_APBCLK_FDIV0_EN_Msk
#define CLK
Pointer to CLK register structure.
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from CPU registers.