Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
clk.c
Go to the documentation of this file.
1 /**************************************************************************/
13 #include "Nano1X2Series.h"
32 void CLK_DisableCKO(void)
33 {
35 }
40 void CLK_DisableCKO0(void)
41 {
42  /* Disable CKO0 clock source */
43  CLK->APBCLK &= (~CLK_APBCLK_FDIV0_EN_Msk);
44 }
45 
50 void CLK_DisableCKO1(void)
51 {
52  /* Disable CKO clock source */
53  CLK->APBCLK &= (~CLK_APBCLK_FDIV1_EN_Msk);
54 }
55 
74 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
75 {
76  CLK_EnableCKO0(u32ClkSrc, u32ClkDiv, u32ClkDivBy1En);
77 }
96 void CLK_EnableCKO0(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
97 {
98  /* Select CKO clock source */
99  CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV0_S_Msk)) | u32ClkSrc;
100 
101  /* CKO = clock source / 2^(u32ClkDiv + 1) */
102  CLK->FRQDIV0 = CLK_FRQDIV0_FDIV_EN_Msk | u32ClkDiv | u32ClkDivBy1En<<CLK_FRQDIV0_DIV1_Pos;
103 
104  /* Enable CKO clock source */
105  CLK->APBCLK |= CLK_APBCLK_FDIV0_EN_Msk;
106 }
107 
126 void CLK_EnableCKO1(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
127 {
128  /* Select CKO clock source */
129  CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_FRQDIV1_S_Msk)) | u32ClkSrc;
130 
131  /* CKO = clock source / 2^(u32ClkDiv + 1) */
132  CLK->FRQDIV1 = CLK_FRQDIV1_FDIV_EN_Msk | u32ClkDiv | u32ClkDivBy1En<<CLK_FRQDIV1_DIV1_Pos;
133 
134  /* Enable CKO clock source */
135  CLK->APBCLK |= CLK_APBCLK_FDIV1_EN_Msk;
136 }
137 
143 void CLK_PowerDown(void)
144 {
145  SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
147  __WFI();
148 }
149 
155 void CLK_Idle(void)
156 {
157  CLK->PWRCTL &= ~(CLK_PWRCTL_PD_EN_Msk );
158  __WFI();
159 }
160 
166 uint32_t CLK_GetHXTFreq(void)
167 {
168  if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN )
169  return __HXT;
170  else
171  return 0;
172 }
173 
179 uint32_t CLK_GetLXTFreq(void)
180 {
181  if(CLK->PWRCTL & CLK_PWRCTL_LXT_EN )
182  return __LXT;
183  else
184  return 0;
185 }
186 
192 uint32_t CLK_GetHCLKFreq(void)
193 {
195  return SystemCoreClock;
196 }
197 
203 uint32_t CLK_GetPCLKFreq(void)
204 {
205  uint32_t Div[]= {1,2,4,8,16,1,1,1};
206  uint32_t PCLK_Div;
207  PCLK_Div = CLK->APB_DIV & CLK_APB_DIV_APBDIV_Msk;
209  return SystemCoreClock/Div[PCLK_Div];
210 }
211 
217 uint32_t CLK_GetCPUFreq(void)
218 {
220  return SystemCoreClock;
221 }
222 
228 uint32_t CLK_GetPLLClockFreq(void)
229 {
230  uint32_t u32Freq =0, u32PLLSrc;
231  uint32_t u32SRC_N,u32PLL_M,u32PllReg;
232 
233  u32PllReg = CLK->PLLCTL;
234 
235  if (u32PllReg & CLK_PLLCTL_PD)
236  return 0; /* PLL is in power down mode */
237 
238  if (u32PllReg & CLK_PLLCTL_PLL_SRC_HIRC)
239  {
240  if(CLK->PLLCTL & CLK_PWRCTL_HIRC_FSEL_Msk)
241  u32PLLSrc =__HIRC16M;
242  else
243  u32PLLSrc =__HIRC12M;
244  }
245  else
246  u32PLLSrc = __HXT;
247 
248  u32SRC_N = (u32PllReg & CLK_PLLCTL_PLL_SRC_N_Msk) >> CLK_PLLCTL_PLL_SRC_N_Pos;
249  u32PLL_M = (u32PllReg & CLK_PLLCTL_PLL_MLP_Msk) >> CLK_PLLCTL_PLL_MLP_Pos;
250 
251  u32Freq = u32PLLSrc * u32PLL_M / (u32SRC_N+1);
252 
253  return u32Freq;
254 }
255 
261 uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
262 {
263  if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN)
264  {
266  }
267  else
268  {
270  }
273  return SystemCoreClock;
274 }
275 
288 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
289 {
290  CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLK_N_Msk) | u32ClkDiv;
291  CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLK_S_Msk) | u32ClkSrc;
293 }
294 
383 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
384 {
385  uint32_t u32tmp=0,u32sel=0,u32div=0;
386 
387  if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk)
388  {
389  u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4);
390  u32tmp = *(volatile uint32_t *)(u32div);
391  u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv;
392  *(volatile uint32_t *)(u32div) = u32tmp;
393  }
394 
395  if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk)
396  {
397  u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4);
398  u32tmp = *(volatile uint32_t *)(u32sel);
399  u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc;
400  *(volatile uint32_t *)(u32sel) = u32tmp;
401  }
402 }
403 
413 void CLK_EnableXtalRC(uint32_t u32ClkMask)
414 {
415  CLK->PWRCTL |= u32ClkMask;
416 }
417 
427 void CLK_DisableXtalRC(uint32_t u32ClkMask)
428 {
429  CLK->PWRCTL &= ~u32ClkMask;
430 }
431 
465 void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
466 {
467  *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
468 }
469 
503 void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
504 {
505  *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
506 }
507 
516 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
517 {
518  uint32_t u32PllCr,u32PLL_N,u32PLL_M,u32PLLReg;
519  if ( u32PllFreq < FREQ_16MHZ)
520  u32PllFreq=FREQ_16MHZ;
521  else if(u32PllFreq > FREQ_32MHZ)
522  u32PllFreq=FREQ_32MHZ;
523 
524  if(u32PllClkSrc == CLK_PLLCTL_PLL_SRC_HXT)
525  {
526  /* PLL source clock from HXT */
527  CLK->PLLCTL &= ~CLK_PLLCTL_PLL_SRC_HIRC;
528  u32PllCr = __HXT;
529  }
530  else
531  {
532  /* PLL source clock from HIRC */
533  CLK->PLLCTL |= CLK_PLLCTL_PLL_SRC_HIRC;
534  if(CLK->PWRCTL & CLK_PWRCTL_HIRC_FSEL_Msk)
535  u32PllCr =__HIRC16M;
536  else
537  u32PllCr =__HIRC12M;
538  }
539 
540 
541  u32PLL_N=u32PllCr/1000000;
542  u32PLL_M=u32PllFreq/1000000;
543  while(1)
544  {
545  if(u32PLL_M<=32 && u32PLL_N<=16 ) break;
546  u32PLL_M >>=1;
547  u32PLL_N >>=1;
548  }
549  u32PLLReg = (u32PLL_M<<CLK_PLLCTL_PLL_MLP_Pos) | ((u32PLL_N-1)<<CLK_PLLCTL_PLL_SRC_N_Pos);
550  CLK->PLLCTL = ( CLK->PLLCTL & ~(CLK_PLLCTL_PLL_MLP_Msk | CLK_PLLCTL_PLL_SRC_N_Msk ) )| u32PLLReg;
551 
552  if(u32PllClkSrc==CLK_PLLCTL_PLL_SRC_HIRC)
553  CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLL_SRC_HIRC) | (CLK_PLLCTL_PLL_SRC_HIRC);
554  else
555  CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLL_SRC_HIRC);
556 
557  CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
558 
559  return CLK_GetPLLClockFreq();
560 }
561 
567 void CLK_DisablePLL(void)
568 {
569  CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
570 }
571 
580 void CLK_SysTickDelay(uint32_t us)
581 {
582  SysTick->LOAD = us * CyclesPerUs;
583  SysTick->VAL = (0x00);
584  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
585 
586  /* Waiting for down-count to zero */
587  while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
588  SysTick->CTRL = 0;
589 }
590 
601 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
602 {
603  SysTick->CTRL=0;
604  if( u32ClkSrc== CLK_CLKSEL0_STCLKSEL_HCLK ) /* Set System Tick clock source */
605  SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
606  else
607  {
608  SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
609  }
610  SysTick->LOAD = u32Count; /* Set System Tick reload value */
611  SysTick->VAL = 0; /* Clear System Tick current value and counter flag */
612  SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; /* Set System Tick counter enabled */
613 }
614 
621 {
622  SysTick->CTRL = 0; /* Set System Tick counter disabled */
623 }
624 
639 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
640 {
641  int32_t i32TimeOutCnt=2160000;
642 
643  while((CLK->CLKSTATUS & u32ClkMask) != u32ClkMask)
644  {
645  if(i32TimeOutCnt-- <= 0)
646  return 0;
647  }
648  return 1;
649 }
650 
651  /* end of group NANO1X2_CLK_EXPORTED_FUNCTIONS */
653  /* end of group NANO1X2_CLK_Driver */
655  /* end of group NANO1X2_Device_Driver */
657 
658 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
659 
void CLK_PowerDown(void)
This function let system enter to Power-down mode.
Definition: clk.c:143
#define FREQ_32MHZ
Definition: clk.h:34
#define CLK_PWRCTL_HXT_EN
Definition: clk.h:38
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:383
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
Definition: clk.c:74
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:166
#define CLK_PLLCTL_PLL_SRC_N_Pos
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
Definition: clk.c:639
#define CLK
Pointer to CLK register structure.
void CLK_Idle(void)
This function let system enter to Idle mode.
Definition: clk.c:155
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
Definition: clk.c:427
#define CLK_PWRCTL_WK_DLY_Msk
#define CLK_PLLCTL_PLL_MLP_Msk
#define MODULE_IP_EN_Pos(x)
Definition: clk.h:242
void CLK_DisableCKO(void)
This function disable frequency output function.
Definition: clk.c:32
#define CLK_CLKSTATUS_PLL_STB_Msk
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
Definition: clk.c:228
#define MODULE_CLKDIV(x)
Definition: clk.h:239
void CLK_EnableCKO1(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
Definition: clk.c:126
void CLK_DisableCKO1(void)
This function disable frequency output function(1).
Definition: clk.c:50
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz.
Definition: clk.c:261
#define __LXT
#define MODULE_NoMsk
Definition: clk.h:243
#define CLK_PWRCTL_HIRC_FSEL_Msk
uint32_t CyclesPerUs
#define MODULE_CLKSEL_Msk(x)
Definition: clk.h:237
#define __HIRC16M
#define __HIRC12M
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
Definition: clk.c:217
#define CLK_CLKSEL2_FRQDIV0_S_Msk
#define CLK_CLKSEL0_HCLK_S_PLL
Definition: clk.h:124
Nano102/112 peripheral access layer header file. This file contains all the peripheral register's def...
#define CLK_FRQDIV1_DIV1_Pos
void CLK_DisableCKO0(void)
This function disable frequency output function.
Definition: clk.c:40
#define MODULE_CLKDIV_Msk(x)
Definition: clk.h:240
uint32_t SystemCoreClock
#define FREQ_16MHZ
Definition: clk.h:35
#define CLK_CLKSEL0_HCLK_S_Msk
void CLK_DisablePLL(void)
This function disable PLL.
Definition: clk.c:567
#define CLK_FRQDIV1_FDIV_EN_Msk
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
Definition: clk.c:503
#define MODULE_CLKDIV_Pos(x)
Definition: clk.h:241
#define CLK_FRQDIV0_FDIV_EN_Msk
#define CLK_HCLK_CLK_DIVIDER(x)
Definition: clk.h:209
#define MODULE_CLKSEL_Pos(x)
Definition: clk.h:238
#define CLK_APB_DIV_APBDIV_Msk
#define CLK_PLLCTL_PLL_MLP_Pos
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from CPU registers.
#define CLK_PWRCTL_PD_EN_Msk
void CLK_EnableCKO0(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
Definition: clk.c:96
#define CLK_PLLCTL_PD
Definition: clk.h:97
#define CLK_APBCLK_FDIV0_EN_Msk
#define CLK_CLKSEL2_FRQDIV1_S_Msk
void CLK_DisableSysTick(void)
Disable System Tick counter.
Definition: clk.c:620
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:192
#define MODULE_CLKSEL(x)
Definition: clk.h:236
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
Definition: clk.c:413
void CLK_SysTickDelay(uint32_t us)
This function execute delay function.
Definition: clk.c:580
#define CLK_PLLCTL_PLL_SRC_HIRC
Definition: clk.h:99
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:179
#define CLK_PWRCTL_LXT_EN
Definition: clk.h:39
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
Definition: clk.c:465
#define CLK_PLLCTL_PLL_SRC_N_Msk
#define CLK_PLLCTL_PLL_SRC_HXT
Definition: clk.h:98
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
Definition: clk.c:601
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
This function set PLL frequency.
Definition: clk.c:516
#define __HXT
#define CLK_CLKDIV0_HCLK_N_Msk
#define CLK_PLLCTL_PD_Msk
#define CLK_APBCLK_FDIV1_EN_Msk
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:288
#define CLK_CLKSEL0_STCLKSEL_HCLK
Definition: clk.h:222
uint32_t CLK_GetPCLKFreq(void)
This function get PCLK frequency. The frequency unit is Hz.
Definition: clk.c:203
#define CLK_FRQDIV0_DIV1_Pos
#define MODULE_APBCLK(x)
Definition: clk.h:235