Nano102_112 Series BSP  V3.03.002
The Board Support Package for Nano102_112 Series
Functions
CLK Exported Functions

Functions

void CLK_DisableCKO (void)
 This function disable frequency output function. More...
 
void CLK_DisableCKO0 (void)
 This function disable frequency output function. More...
 
void CLK_DisableCKO1 (void)
 This function disable frequency output function(1). More...
 
void CLK_EnableCKO (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
 This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. More...
 
void CLK_EnableCKO0 (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
 This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. More...
 
void CLK_EnableCKO1 (uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
 This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. (1) More...
 
void CLK_PowerDown (void)
 This function let system enter to Power-down mode. More...
 
void CLK_Idle (void)
 This function let system enter to Idle mode. More...
 
uint32_t CLK_GetHXTFreq (void)
 This function get external high frequency crystal frequency. The frequency unit is Hz. More...
 
uint32_t CLK_GetLXTFreq (void)
 This function get external low frequency crystal frequency. The frequency unit is Hz. More...
 
uint32_t CLK_GetHCLKFreq (void)
 This function get HCLK frequency. The frequency unit is Hz. More...
 
uint32_t CLK_GetPCLKFreq (void)
 This function get PCLK frequency. The frequency unit is Hz. More...
 
uint32_t CLK_GetCPUFreq (void)
 This function get CPU frequency. The frequency unit is Hz. More...
 
uint32_t CLK_GetPLLClockFreq (void)
 This function get PLL frequency. The frequency unit is Hz. More...
 
uint32_t CLK_SetCoreClock (uint32_t u32Hclk)
 This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz. More...
 
void CLK_SetHCLK (uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set HCLK clock source and HCLK clock divider. More...
 
void CLK_SetModuleClock (uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
 This function set selected module clock source and module clock divider. More...
 
void CLK_SetSysTickClockSrc (uint32_t u32ClkSrc)
 
void CLK_EnableXtalRC (uint32_t u32ClkMask)
 This function enable clock source. More...
 
void CLK_DisableXtalRC (uint32_t u32ClkMask)
 This function disable clock source. More...
 
void CLK_EnableModuleClock (uint32_t u32ModuleIdx)
 This function enable module clock. More...
 
void CLK_DisableModuleClock (uint32_t u32ModuleIdx)
 This function disable module clock. More...
 
uint32_t CLK_EnablePLL (uint32_t u32PllClkSrc, uint32_t u32PllFreq)
 This function set PLL frequency. More...
 
void CLK_DisablePLL (void)
 This function disable PLL. More...
 
void CLK_SysTickDelay (uint32_t us)
 This function execute delay function. More...
 
void CLK_EnableSysTick (uint32_t u32ClkSrc, uint32_t u32Count)
 Enable System Tick counter. More...
 
void CLK_DisableSysTick (void)
 Disable System Tick counter. More...
 
uint32_t CLK_WaitClockReady (uint32_t u32ClkMask)
 This function check selected clock source status. More...
 

Detailed Description

Function Documentation

◆ CLK_DisableCKO()

void CLK_DisableCKO ( void  )

This function disable frequency output function.

Parameters
None
Returns
None

Definition at line 32 of file clk.c.

◆ CLK_DisableCKO0()

void CLK_DisableCKO0 ( void  )

This function disable frequency output function.

Returns
None

Definition at line 40 of file clk.c.

◆ CLK_DisableCKO1()

void CLK_DisableCKO1 ( void  )

This function disable frequency output function(1).

Returns
None

Definition at line 50 of file clk.c.

◆ CLK_DisableModuleClock()

void CLK_DisableModuleClock ( uint32_t  u32ModuleIdx)

◆ CLK_DisablePLL()

void CLK_DisablePLL ( void  )

This function disable PLL.

Parameters
None
Returns
None

Definition at line 567 of file clk.c.

◆ CLK_DisableSysTick()

void CLK_DisableSysTick ( void  )

Disable System Tick counter.

Returns
None

This function disable System Tick counter.

Definition at line 620 of file clk.c.

◆ CLK_DisableXtalRC()

void CLK_DisableXtalRC ( uint32_t  u32ClkMask)

This function disable clock source.

Parameters
u32ClkMaskis clock source mask. Including:
Returns
None

Definition at line 427 of file clk.c.

◆ CLK_EnableCKO()

void CLK_EnableCKO ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv,
uint32_t  u32ClkDivBy1En 
)

This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider.

Parameters
[in]u32ClkSrcis frequency divider function clock source
[in]u32ClkDivis divider output frequency selection.
[in]u32ClkDivBy1Enis frequency divided by one enable.
Returns
None

Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. The formula is: CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) This function is just used to set CKO clock. User must enable I/O for CKO clock output pin by themselves.

Definition at line 74 of file clk.c.

◆ CLK_EnableCKO0()

void CLK_EnableCKO0 ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv,
uint32_t  u32ClkDivBy1En 
)

This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider.

Parameters
u32ClkSrcis frequency divider function clock source
u32ClkDivis divider output frequency selection.
u32ClkDivBy1Enis frequency divided by one enable.
Returns
None

Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. The formula is: CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) This function is just used to set CKO clock. User must enable I/O for CKO clock output pin by themselves.

Definition at line 96 of file clk.c.

◆ CLK_EnableCKO1()

void CLK_EnableCKO1 ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv,
uint32_t  u32ClkDivBy1En 
)

This function enable frequency divider module clock, enable frequency divider clock function and configure frequency divider. (1)

Parameters
[in]u32ClkSrcis frequency divider function clock source
[in]u32ClkDivis system reset source
[in]u32ClkDivBy1Enis frequency divided by one enable.
Returns
None

Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. The formula is: CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) This function is just used to set CKO clock. User must enable I/O for CKO clock output pin by themselves.

Definition at line 126 of file clk.c.

◆ CLK_EnableModuleClock()

void CLK_EnableModuleClock ( uint32_t  u32ModuleIdx)

◆ CLK_EnablePLL()

uint32_t CLK_EnablePLL ( uint32_t  u32PllClkSrc,
uint32_t  u32PllFreq 
)

This function set PLL frequency.

Parameters
[in]u32PllClkSrcis PLL clock source. Including :
[in]u32PllFreqis PLL frequency
Returns
None

Definition at line 516 of file clk.c.

◆ CLK_EnableSysTick()

void CLK_EnableSysTick ( uint32_t  u32ClkSrc,
uint32_t  u32Count 
)

Enable System Tick counter.

Parameters
[in]u32ClkSrcis System Tick clock source. Including:
[in]u32Countis System Tick reload value. It should be 0x1~0xFFFFFF.
Returns
None

This function set System Tick clock source, reload value, enable System Tick counter and interrupt. The register write-protection function should be disabled before using this function.

Definition at line 601 of file clk.c.

◆ CLK_EnableXtalRC()

void CLK_EnableXtalRC ( uint32_t  u32ClkMask)

This function enable clock source.

Parameters
[in]u32ClkMaskis clock source mask. Including:
Returns
None

Definition at line 413 of file clk.c.

◆ CLK_GetCPUFreq()

uint32_t CLK_GetCPUFreq ( void  )

This function get CPU frequency. The frequency unit is Hz.

Parameters
None
Returns
CPU frequency

Definition at line 217 of file clk.c.

◆ CLK_GetHCLKFreq()

uint32_t CLK_GetHCLKFreq ( void  )

This function get HCLK frequency. The frequency unit is Hz.

Parameters
None
Returns
HCLK frequency

Definition at line 192 of file clk.c.

◆ CLK_GetHXTFreq()

uint32_t CLK_GetHXTFreq ( void  )

This function get external high frequency crystal frequency. The frequency unit is Hz.

Parameters
None
Returns
None

Definition at line 166 of file clk.c.

◆ CLK_GetLXTFreq()

uint32_t CLK_GetLXTFreq ( void  )

This function get external low frequency crystal frequency. The frequency unit is Hz.

Parameters
None
Returns
LXT frequency

Definition at line 179 of file clk.c.

◆ CLK_GetPCLKFreq()

uint32_t CLK_GetPCLKFreq ( void  )

This function get PCLK frequency. The frequency unit is Hz.

Parameters
None
Returns
PCLK frequency

Definition at line 203 of file clk.c.

◆ CLK_GetPLLClockFreq()

uint32_t CLK_GetPLLClockFreq ( void  )

This function get PLL frequency. The frequency unit is Hz.

Parameters
None
Returns
PLL frequency

Definition at line 228 of file clk.c.

◆ CLK_Idle()

void CLK_Idle ( void  )

This function let system enter to Idle mode.

Parameters
None
Returns
None

Definition at line 155 of file clk.c.

◆ CLK_PowerDown()

void CLK_PowerDown ( void  )

This function let system enter to Power-down mode.

Parameters
None
Returns
None

Definition at line 143 of file clk.c.

◆ CLK_SetCoreClock()

uint32_t CLK_SetCoreClock ( uint32_t  u32Hclk)

This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 32 MHz.

Parameters
[in]u32Hclkis HCLK frequency
Returns
None

Definition at line 261 of file clk.c.

◆ CLK_SetHCLK()

void CLK_SetHCLK ( uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv 
)

This function set HCLK clock source and HCLK clock divider.

Parameters
[in]u32ClkSrcis HCLK clock source. Including :
[in]u32ClkDivis HCLK clock divider. Including :
Returns
None

Definition at line 288 of file clk.c.

◆ CLK_SetModuleClock()

void CLK_SetModuleClock ( uint32_t  u32ModuleIdx,
uint32_t  u32ClkSrc,
uint32_t  u32ClkDiv 
)

This function set selected module clock source and module clock divider.

Parameters
[in]u32ModuleIdxis module index.
[in]u32ClkSrcis module clock source.
[in]u32ClkDivis module clock divider.
Returns
None

Valid parameter combinations listed in following table:

Module index Clock source Divider
SC1_MODULE CLK_CLKSEL2_SC_S_HXT CLK_SC1_CLK_DIVIDER(x)
SC1_MODULE CLK_CLKSEL2_SC_S_PLL CLK_SC1_CLK_DIVIDER(x)
SC1_MODULE CLK_CLKSEL2_SC_S_HIRC CLK_SC1_CLK_DIVIDER(x)
SC1_MODULE CLK_CLKSEL2_SC_S_HCLK CLK_SC1_CLK_DIVIDER(x)
SC0_MODULE CLK_CLKSEL2_SC_S_HXT CLK_SC0_CLK_DIVIDER(x)
SC0_MODULE CLK_CLKSEL2_SC_S_PLL CLK_SC0_CLK_DIVIDER(x)
SC0_MODULE CLK_CLKSEL2_SC_S_HIRC CLK_SC0_CLK_DIVIDER(x)
SC0_MODULE CLK_CLKSEL2_SC_S_HCLK CLK_SC0_CLK_DIVIDER(x)
ADC_MODULE CLK_CLKSEL1_ADC_S_HXT CLK_ADC_CLK_DIVIDER(x)
ADC_MODULE CLK_CLKSEL1_ADC_S_LXT CLK_ADC_CLK_DIVIDER(x)
ADC_MODULE CLK_CLKSEL1_ADC_S_PLL CLK_ADC_CLK_DIVIDER(x)
ADC_MODULE CLK_CLKSEL1_ADC_S_HIRC CLK_ADC_CLK_DIVIDER(x)
ADC_MODULE CLK_CLKSEL1_ADC_S_HCLK CLK_ADC_CLK_DIVIDER(x)
LCD_MODULE CLK_CLKSEL1_LCD_S_LXT x
PWM0_CH23_MODULE CLK_CLKSEL1_PWM0_CH23_S_HXT x
PWM0_CH23_MODULE CLK_CLKSEL1_PWM0_CH23_S_LXT x
PWM0_CH23_MODULE CLK_CLKSEL1_PWM0_CH23_S_HCLK x
PWM0_CH23_MODULE CLK_CLKSEL1_PWM0_CH23_S_HIRC x
PWM0_CH01_MODULE CLK_CLKSEL1_PWM0_CH01_S_HXT x
PWM0_CH01_MODULE CLK_CLKSEL1_PWM0_CH01_S_LXT x
PWM0_CH01_MODULE CLK_CLKSEL1_PWM0_CH01_S_HCLK x
PWM0_CH01_MODULE CLK_CLKSEL1_PWM0_CH01_S_HIRC x
UART1_MODULE CLK_CLKSEL1_UART_S_HXT CLK_UART_CLK_DIVIDER(x)
UART1_MODULE CLK_CLKSEL1_UART_S_LXT CLK_UART_CLK_DIVIDER(x)
UART1_MODULE CLK_CLKSEL1_UART_S_PLL CLK_UART_CLK_DIVIDER(x)
UART1_MODULE CLK_CLKSEL1_UART_S_HIRC CLK_UART_CLK_DIVIDER(x)
UART0_MODULE CLK_CLKSEL1_UART_S_HXT CLK_UART_CLK_DIVIDER(x)
UART0_MODULE CLK_CLKSEL1_UART_S_LXT CLK_UART_CLK_DIVIDER(x)
UART0_MODULE CLK_CLKSEL1_UART_S_PLL CLK_UART_CLK_DIVIDER(x)
UART0_MODULE CLK_CLKSEL1_UART_S_HIRC CLK_UART_CLK_DIVIDER(x)
SPI1_MODULE CLK_CLKSEL2_SPI1_S_PLL x
SPI1_MODULE CLK_CLKSEL2_SPI1_S_HCLK x
SPI0_MODULE CLK_CLKSEL2_SPI0_S_PLL x
SPI0_MODULE CLK_CLKSEL2_SPI0_S_HCLK x
ACMP_MODULE x x
I2C1_MODULE x x
I2C0_MODULE x x
FDIV1_MODULE CLK_CLKSEL2_FRQDIV1_S_HXT x
FDIV1_MODULE CLK_CLKSEL2_FRQDIV1_S_LXT x
FDIV1_MODULE CLK_CLKSEL2_FRQDIV1_S_HCLK x
FDIV1_MODULE CLK_CLKSEL2_FRQDIV1_S_HIRC x
FDIV0_MODULE CLK_CLKSEL2_FRQDIV0_S_HXT x
FDIV0_MODULE CLK_CLKSEL2_FRQDIV0_S_LXT x
FDIV0_MODULE CLK_CLKSEL2_FRQDIV0_S_HCLK x
FDIV0_MODULE CLK_CLKSEL2_FRQDIV0_S_HIRC x
FDIV_MODULE CLK_CLKSEL2_FRQDIV_S_HXT x
FDIV_MODULE CLK_CLKSEL2_FRQDIV_S_LXT x
FDIV_MODULE CLK_CLKSEL2_FRQDIV_S_HCLK x
FDIV_MODULE CLK_CLKSEL2_FRQDIV_S_HIRC x
TMR3_MODULE CLK_CLKSEL2_TMR3_S_HXT CLK_TMR3_CLK_DIVIDER(x)
TMR3_MODULE CLK_CLKSEL2_TMR3_S_LXT CLK_TMR3_CLK_DIVIDER(x)
TMR3_MODULE CLK_CLKSEL2_TMR3_S_LIRC CLK_TMR3_CLK_DIVIDER(x)
TMR3_MODULE CLK_CLKSEL2_TMR3_S_EXT CLK_TMR3_CLK_DIVIDER(x)
TMR3_MODULE CLK_CLKSEL2_TMR3_S_HIRC CLK_TMR3_CLK_DIVIDER(x)
TMR3_MODULE CLK_CLKSEL2_TMR3_S_HCLK CLK_TMR3_CLK_DIVIDER(x)
TMR2_MODULE CLK_CLKSEL2_TMR2_S_HXT CLK_TMR2_CLK_DIVIDER(x)
TMR2_MODULE CLK_CLKSEL2_TMR2_S_LXT CLK_TMR2_CLK_DIVIDER(x)
TMR2_MODULE CLK_CLKSEL2_TMR2_S_LIRC CLK_TMR2_CLK_DIVIDER(x)
TMR2_MODULE CLK_CLKSEL2_TMR2_S_EXT CLK_TMR2_CLK_DIVIDER(x)
TMR2_MODULE CLK_CLKSEL2_TMR2_S_HIRC CLK_TMR2_CLK_DIVIDER(x)
TMR2_MODULE CLK_CLKSEL2_TMR2_S_HCLK CLK_TMR2_CLK_DIVIDER(x)
TMR1_MODULE CLK_CLKSEL1_TMR1_S_HXT CLK_TMR1_CLK_DIVIDER(x)
TMR1_MODULE CLK_CLKSEL1_TMR1_S_LXT CLK_TMR1_CLK_DIVIDER(x)
TMR1_MODULE CLK_CLKSEL1_TMR1_S_LIRC CLK_TMR1_CLK_DIVIDER(x)
TMR1_MODULE CLK_CLKSEL1_TMR1_S_EXT CLK_TMR1_CLK_DIVIDER(x)
TMR1_MODULE CLK_CLKSEL1_TMR1_S_HIRC CLK_TMR1_CLK_DIVIDER(x)
TMR1_MODULE CLK_CLKSEL1_TMR1_S_HCLK CLK_TMR1_CLK_DIVIDER(x)
TMR0_MODULE CLK_CLKSEL1_TMR0_S_HXT CLK_TMR0_CLK_DIVIDER(x)
TMR0_MODULE CLK_CLKSEL1_TMR0_S_LXT CLK_TMR0_CLK_DIVIDER(x)
TMR0_MODULE CLK_CLKSEL1_TMR0_S_LIRC CLK_TMR0_CLK_DIVIDER(x)
TMR0_MODULE CLK_CLKSEL1_TMR0_S_EXT CLK_TMR0_CLK_DIVIDER(x)
TMR0_MODULE CLK_CLKSEL1_TMR0_S_HIRC CLK_TMR0_CLK_DIVIDER(x)
TMR0_MODULE CLK_CLKSEL1_TMR0_S_HCLK CLK_TMR0_CLK_DIVIDER(x)
RTC_MODULE x x
WDT_MODULE x x

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Definition at line 383 of file clk.c.

◆ CLK_SetSysTickClockSrc()

void CLK_SetSysTickClockSrc ( uint32_t  u32ClkSrc)

◆ CLK_SysTickDelay()

void CLK_SysTickDelay ( uint32_t  us)

This function execute delay function.

Parameters
[in]usDelay time. The Max value is 2^24 / CPU Clock(MHz). Ex: 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
Returns
None

Use the SysTick to generate the delay time and the UNIT is in us. The SysTick clock source is from HCLK, i.e the same as system core clock.

Definition at line 580 of file clk.c.

◆ CLK_WaitClockReady()

uint32_t CLK_WaitClockReady ( uint32_t  u32ClkMask)

This function check selected clock source status.

Parameters
[in]u32ClkMaskis selected clock source. Including
Returns
0 clock is not stable 1 clock is stable

To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms)

Definition at line 639 of file clk.c.