NANO103 BSP V3.01.004
The Board Support Package for Nano103 Series
Nano103.h
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1/**************************************************************************/
52#ifndef __NANO103_H__
53#define __NANO103_H__
54
55#ifdef __cplusplus
56extern "C" {
57#endif
58
69/******************************************************************************/
70/* Processor and Core Peripherals */
71/******************************************************************************/
80typedef enum IRQn
81{
82 /****** Cortex-M0 Processor Exceptions Numbers *****************************************/
83
90 /****** NANO103 specific Interrupt Numbers ***********************************************/
110 SC0_IRQn = 21,
111 SC1_IRQn = 22,
116 ADC_IRQn = 29,
118 RTC_IRQn = 31
120
121
122/*
123 * ==========================================================================
124 * ----------- Processor and Core Peripheral Section ------------------------
125 * ==========================================================================
126 */
127
128/* Configuration of the Cortex-M0 Processor and Core Peripherals */
129#define __CM0_REV 0x0201
130#define __NVIC_PRIO_BITS 2
131#define __Vendor_SysTickConfig 0
132#define __MPU_PRESENT 0
133#define __FPU_PRESENT 0 /* end of group NANO103_CMSIS */
136
137
138#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
139#include "system_Nano103.h" /* NANO103 Series System include file */
140#include <stdint.h>
141
142/******************************************************************************/
143/* Device Specific Peripheral registers structures */
144/******************************************************************************/
150#if defined ( __CC_ARM )
151#pragma anon_unions
152#endif
153
154
155/*---------------------- INT Controller -------------------------*/
161typedef struct
162{
163
164
410 __I uint32_t IRQ0_SRC;
411 __I uint32_t IRQ1_SRC;
412 __I uint32_t IRQ2_SRC;
413 __I uint32_t IRQ3_SRC;
414 __I uint32_t IRQ4_SRC;
415 __I uint32_t IRQ5_SRC;
416 __I uint32_t IRQ6_SRC;
417 __I uint32_t IRQ7_SRC;
418 __I uint32_t IRQ8_SRC;
419 __I uint32_t IRQ9_SRC;
420 __I uint32_t IRQ10_SRC;
421 __I uint32_t IRQ11_SRC;
422 __I uint32_t IRQ12_SRC;
423 __I uint32_t IRQ13_SRC;
424 __I uint32_t IRQ14_SRC;
425 __I uint32_t IRQ15_SRC;
426 __I uint32_t IRQ16_SRC;
427 __I uint32_t IRQ17_SRC;
428 __I uint32_t IRQ18_SRC;
429 __I uint32_t IRQ19_SRC;
430 __I uint32_t IRQ20_SRC;
431 __I uint32_t IRQ21_SRC;
432 __I uint32_t IRQ22_SRC;
433 __I uint32_t IRQ23_SRC;
434 __I uint32_t IRQ24_SRC;
435 __I uint32_t IRQ25_SRC;
436 __I uint32_t IRQ26_SRC;
437 __I uint32_t IRQ27_SRC;
438 __I uint32_t IRQ28_SRC;
439 __I uint32_t IRQ29_SRC;
440 __I uint32_t IRQ30_SRC;
441 __I uint32_t IRQ31_SRC;
442 __IO uint32_t NMI_SEL;
443 __IO uint32_t MCU_IRQ;
446} INT_T;
447
453#define INT_IRQ0_SRC_INT_SRC_Pos (0)
454#define INT_IRQ0_SRC_INT_SRC_Msk (0xful << INT_IRQ0_SRC_INT_SRC_Pos)
456#define INT_IRQ1_SRC_INT_SRC_Pos (0)
457#define INT_IRQ1_SRC_INT_SRC_Msk (0xful << INT_IRQ1_SRC_INT_SRC_Pos)
459#define INT_IRQ2_SRC_INT_SRC_Pos (0)
460#define INT_IRQ2_SRC_INT_SRC_Msk (0xful << INT_IRQ2_SRC_INT_SRC_Pos)
462#define INT_IRQ3_SRC_INT_SRC_Pos (0)
463#define INT_IRQ3_SRC_INT_SRC_Msk (0xful << INT_IRQ3_SRC_INT_SRC_Pos)
465#define INT_IRQ4_SRC_INT_SRC_Pos (0)
466#define INT_IRQ4_SRC_INT_SRC_Msk (0xful << INT_IRQ4_SRC_INT_SRC_Pos)
468#define INT_IRQ5_SRC_INT_SRC_Pos (0)
469#define INT_IRQ5_SRC_INT_SRC_Msk (0xful << INT_IRQ5_SRC_INT_SRC_Pos)
471#define INT_IRQ6_SRC_INT_SRC_Pos (0)
472#define INT_IRQ6_SRC_INT_SRC_Msk (0xful << INT_IRQ6_SRC6_INT_SRC_Pos)
474#define INT_IRQ7_SRC_INT_SRC_Pos (0)
475#define INT_IRQ7_SRC_INT_SRC_Msk (0xful << INT_IRQ7_SRC_INT_SRC_Pos)
477#define INT_IRQ8_SRC_INT_SRC_Pos (0)
478#define INT_IRQ8_SRC_INT_SRC_Msk (0xful << INT_IRQ8_SRC_INT_SRC_Pos)
480#define INT_IRQ9_SRC_INT_SRC_Pos (0)
481#define INT_IRQ9_SRC_INT_SRC_Msk (0xful << INT_IRQ9_SRC_INT_SRC_Pos)
483#define INT_IRQ10_SRC_INT_SRC_Pos (0)
484#define INT_IRQ10_SRC_INT_SRC_Msk (0xful << INT_IRQ10_SRC_INT_SRC_Pos)
486#define INT_IRQ11_SRC_INT_SRC_Pos (0)
487#define INT_IRQ11_SRC_INT_SRC_Msk (0xful << INT_IRQ11_SRC_INT_SRC_Pos)
489#define INT_IRQ12_SRC_INT_SRC_Pos (0)
490#define INT_IRQ12_SRC_INT_SRC_Msk (0xful << INT_IRQ12_SRC_INT_SRC_Pos)
492#define INT_IRQ13_SRC_INT_SRC_Pos (0)
493#define INT_IRQ13_SRC_INT_SRC_Msk (0xful << INT_IRQ13_SRC_INT_SRC_Pos)
495#define INT_IRQ14_SRC_INT_SRC_Pos (0)
496#define INT_IRQ14_SRC_INT_SRC_Msk (0xful << INT_IRQ14_SRC_INT_SRC_Pos)
498#define INT_IRQ15_SRC_INT_SRC_Pos (0)
499#define INT_IRQ15_SRC_INT_SRC_Msk (0xful << INT_IRQ15_SRC_INT_SRC_Pos)
501#define INT_IRQ16_SRC_INT_SRC_Pos (0)
502#define INT_IRQ16_SRC_INT_SRC_Msk (0xful << INT_IRQ16_SRC_INT_SRC_Pos)
504#define INT_IRQ17_SRC_INT_SRC_Pos (0)
505#define INT_IRQ17_SRC_INT_SRC_Msk (0xful << INT_IRQ17_SRC_INT_SRC_Pos)
507#define INT_IRQ18_SRC_INT_SRC_Pos (0)
508#define INT_IRQ18_SRC_INT_SRC_Msk (0xful << INT_IRQ18_SRC_INT_SRC_Pos)
510#define INT_IRQ19_SRC_INT_SRC_Pos (0)
511#define INT_IRQ19_SRC_INT_SRC_Msk (0xful << INT_IRQ19_SRC_INT_SRC_Pos)
513#define INT_IRQ20_SRC_INT_SRC_Pos (0)
514#define INT_IRQ20_SRC_INT_SRC_Msk (0xful << INT_IRQ20_SRC_INT_SRC_Pos)
516#define INT_IRQ21_SRC_INT_SRC_Pos (0)
517#define INT_IRQ21_SRC_INT_SRC_Msk (0xful << INT_IRQ21_SRC_INT_SRC_Pos)
519#define INT_IRQ22_SRC_INT_SRC_Pos (0)
520#define INT_IRQ22_SRC_INT_SRC_Msk (0xful << INT_IRQ22_SRC_INT_SRC_Pos)
522#define INT_IRQ23_SRC_INT_SRC_Pos (0)
523#define INT_IRQ23_SRC_INT_SRC_Msk (0xful << INT_IRQ23_SRC_INT_SRC_Pos)
525#define INT_IRQ24_SRC_INT_SRC_Pos (0)
526#define INT_IRQ24_SRC_INT_SRC_Msk (0xful << INT_IRQ24_SRC_INT_SRC_Pos)
528#define INT_IRQ25_SRC_INT_SRC_Pos (0)
529#define INT_IRQ25_SRC_INT_SRC_Msk (0xful << INT_IRQ25_SRC_INT_SRC_Pos)
531#define INT_IRQ26_SRC_INT_SRC_Pos (0)
532#define INT_IRQ26_SRC_INT_SRC_Msk (0xful << INT_IRQ26_SRC_INT_SRC_Pos)
534#define INT_IRQ27_SRC_INT_SRC_Pos (0)
535#define INT_IRQ27_SRC_INT_SRC_Msk (0xful << INT_IRQ27_SRC_INT_SRC_Pos)
537#define INT_IRQ28_SRC_INT_SRC_Pos (0)
538#define INT_IRQ28_SRC_INT_SRC_Msk (0xful << INT_IRQ28_SRC_INT_SRC_Pos)
540#define INT_IRQ29_SRC_INT_SRC_Pos (0)
541#define INT_IRQ29_SRC_INT_SRC_Msk (0xful << INT_IRQ29_SRC_INT_SRC_Pos)
543#define INT_IRQ30_SRC_INT_SRC_Pos (0)
544#define INT_IRQ30_SRC_INT_SRC_Msk (0xful << INT_IRQ30_SRC_INT_SRC_Pos)
546#define INT_IRQ31_SRC_INT_SRC_Pos (0)
547#define INT_IRQ31_SRC_INT_SRC_Msk (0xful << INT_IRQ31_SRC_INT_SRC_Pos)
549#define INT_NMI_SEL_NMI_SEL_Pos (0)
550#define INT_NMI_SEL_NMI_SEL_Msk (0x1ful << INT_NMI_SEL_NMI_SEL_Pos)
552#define INT_MCU_IRQ_MCU_IRQ_Pos (0)
553#define INT_MCU_IRQ_MCU_IRQ_Msk (0xfffffffful << INT_MCU_IRQ_MCU_IRQ_Pos) /* INT_CONST */ /* end of INT register group */
557
558
559/*---------------------- System Manger Controller -------------------------*/
565typedef struct
566{
567
568
1548 __I uint32_t PDID;
1549 __IO uint32_t RSTSTS;
1550 __IO uint32_t IPRST1;
1551 __IO uint32_t IPRST2;
1553 __I uint32_t RESERVE[1];
1555 __IO uint32_t MISCCTL;
1557 __I uint32_t RESERVE0[2];
1559 __IO uint32_t TEMPCTL;
1561 __I uint32_t RESERVE1[1];
1563 __IO uint32_t RCCFCTL;
1565 __I uint32_t RESERVE2[1];
1567 __IO uint32_t GPA_MFPL;
1568 __IO uint32_t GPA_MFPH;
1569 __IO uint32_t GPB_MFPL;
1570 __IO uint32_t GPB_MFPH;
1571 __IO uint32_t GPC_MFPL;
1572 __IO uint32_t GPC_MFPH;
1573 __IO uint32_t GPD_MFPL;
1574 __IO uint32_t GPD_MFPH;
1575 __IO uint32_t GPE_MFPL;
1577 __I uint32_t RESERVE3[1];
1579 __IO uint32_t GPF_MFPL;
1581 __I uint32_t RESERVE4[1];
1583 __IO uint32_t PORCTL;
1584 __IO uint32_t BODCTL;
1586 __I uint32_t RESERVE5[1];
1588 __IO uint32_t IVREFCTL;
1589 __IO uint32_t LDOCTL;
1590 __IO uint32_t BATDIVCTL;
1592 __I uint32_t RESERVE6[1];
1594 __I uint32_t WKSTS;
1595 __IO uint32_t IRC0TCTL;
1596 __IO uint32_t IRC0TIEN;
1597 __IO uint32_t IRC0TISTS;
1599 __I uint32_t RESERVE7[1];
1601 __IO uint32_t IRC1TCTL;
1602 __IO uint32_t IRC1TIEN;
1603 __IO uint32_t IRC1TISTS;
1605 __I uint32_t RESERVE8[1];
1607 __IO uint32_t MIRCTCTL;
1608 __IO uint32_t MIRCTIEN;
1609 __IO uint32_t MIRCTISTS;
1611 __I uint32_t RESERVE9[21];
1613 __O uint32_t REGLCTL;
1615 __I uint32_t RESERVE10[7];
1617 __IO uint32_t RPDBCLK;
1619} SYS_T;
1620
1626#define SYS_PDID_PDID_Pos (0)
1627#define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos)
1629#define SYS_RSTSTS_PORF_Pos (0)
1630#define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos)
1632#define SYS_RSTSTS_PINRF_Pos (1)
1633#define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos)
1635#define SYS_RSTSTS_WDTRF_Pos (2)
1636#define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos)
1638#define SYS_RSTSTS_LVRF_Pos (3)
1639#define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos)
1641#define SYS_RSTSTS_BODRF_Pos (4)
1642#define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos)
1644#define SYS_RSTSTS_SYSRF_Pos (5)
1645#define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos)
1647#define SYS_RSTSTS_CPURF_Pos (7)
1648#define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos)
1650#define SYS_RSTSTS_LOCKRF_Pos (8)
1651#define SYS_RSTSTS_LOCKRF_Msk (0x1ul << SYS_RSTSTS_LOCKRF_Pos)
1653#define SYS_IPRST1_CHIPRST_Pos (0)
1654#define SYS_IPRST1_CHIPRST_Msk (0x1ul << SYS_IPRST1_CHIPRST_Pos)
1656#define SYS_IPRST1_CPURST_Pos (1)
1657#define SYS_IPRST1_CPURST_Msk (0x1ul << SYS_IPRST1_CPURST_Pos)
1659#define SYS_IPRST1_PDMARST_Pos (2)
1660#define SYS_IPRST1_PDMARST_Msk (0x1ul << SYS_IPRST1_PDMARST_Pos)
1662#define SYS_IPRST2_GPIORST_Pos (1)
1663#define SYS_IPRST2_GPIORST_Msk (0x1ul << SYS_IPRST2_GPIORST_Pos)
1665#define SYS_IPRST2_TMR0RST_Pos (2)
1666#define SYS_IPRST2_TMR0RST_Msk (0x1ul << SYS_IPRST2_TMR0RST_Pos)
1668#define SYS_IPRST2_TMR1RST_Pos (3)
1669#define SYS_IPRST2_TMR1RST_Msk (0x1ul << SYS_IPRST2_TMR1RST_Pos)
1671#define SYS_IPRST2_TMR2RST_Pos (4)
1672#define SYS_IPRST2_TMR2RST_Msk (0x1ul << SYS_IPRST2_TMR2RST_Pos)
1674#define SYS_IPRST2_TMR3RST_Pos (5)
1675#define SYS_IPRST2_TMR3RST_Msk (0x1ul << SYS_IPRST2_TMR3RST_Pos)
1677#define SYS_IPRST2_I2C0RST_Pos (8)
1678#define SYS_IPRST2_I2C0RST_Msk (0x1ul << SYS_IPRST2_I2C0RST_Pos)
1680#define SYS_IPRST2_I2C1RST_Pos (9)
1681#define SYS_IPRST2_I2C1RST_Msk (0x1ul << SYS_IPRST2_I2C1RST_Pos)
1683#define SYS_IPRST2_SPI0RST_Pos (12)
1684#define SYS_IPRST2_SPI0RST_Msk (0x1ul << SYS_IPRST2_SPI0RST_Pos)
1686#define SYS_IPRST2_SPI1RST_Pos (13)
1687#define SYS_IPRST2_SPI1RST_Msk (0x1ul << SYS_IPRST2_SPI1RST_Pos)
1689#define SYS_IPRST2_SPI2RST_Pos (14)
1690#define SYS_IPRST2_SPI2RST_Msk (0x1ul << SYS_IPRST2_SPI2RST_Pos)
1692#define SYS_IPRST2_SPI3RST_Pos (15)
1693#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos)
1695#define SYS_IPRST2_UART0RST_Pos (16)
1696#define SYS_IPRST2_UART0RST_Msk (0x1ul << SYS_IPRST2_UART0RST_Pos)
1698#define SYS_IPRST2_UART1RST_Pos (17)
1699#define SYS_IPRST2_UART1RST_Msk (0x1ul << SYS_IPRST2_UART1RST_Pos)
1701#define SYS_IPRST2_PWM0RST_Pos (20)
1702#define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos)
1704#define SYS_IPRST2_ACMP0RST_Pos (22)
1705#define SYS_IPRST2_ACMP0RST_Msk (0x1ul << SYS_IPRST2_ACMP0RST_Pos)
1707#define SYS_IPRST2_ADCRST_Pos (28)
1708#define SYS_IPRST2_ADCRST_Msk (0x1ul << SYS_IPRST2_ADCRST_Pos)
1710#define SYS_IPRST2_SC0RST_Pos (30)
1711#define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos)
1713#define SYS_IPRST2_SC1RST_Pos (31)
1714#define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos)
1716#define SYS_MISCCTL_POR33DIS_Pos (6)
1717#define SYS_MISCCTL_POR33DIS_Msk (0x1ul << SYS_MISCCTL_POR33DIS_Pos)
1719#define SYS_MISCCTL_POR18DIS_Pos (7)
1720#define SYS_MISCCTL_POR18DIS_Msk (0x1ul << SYS_MISCCTL_POR18DIS_Pos)
1722#define SYS_TEMPCTL_VTEMPEN_Pos (0)
1723#define SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos)
1725#define SYS_RCCFCTL_HIRC0FEN_Pos (0)
1726#define SYS_RCCFCTL_HIRC0FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC0FEN_Pos)
1728#define SYS_RCCFCTL_HIRC1FEN_Pos (1)
1729#define SYS_RCCFCTL_HIRC1FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC1FEN_Pos)
1731#define SYS_RCCFCTL_MRCFEN_Pos (2)
1732#define SYS_RCCFCTL_MRCFEN_Msk (0x1ul << SYS_RCCFCTL_MRCFEN_Pos)
1734#define SYS_GPA_MFPL_PA0MFP_Pos (0)
1735#define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos)
1737#define SYS_GPA_MFPL_PA1MFP_Pos (4)
1738#define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos)
1740#define SYS_GPA_MFPL_PA2MFP_Pos (8)
1741#define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos)
1743#define SYS_GPA_MFPL_PA3MFP_Pos (12)
1744#define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos)
1746#define SYS_GPA_MFPL_PA4MFP_Pos (16)
1747#define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos)
1749#define SYS_GPA_MFPL_PA5MFP_Pos (20)
1750#define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos)
1752#define SYS_GPA_MFPL_PA6MFP_Pos (24)
1753#define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos)
1755#define SYS_GPA_MFPH_PA8MFP_Pos (0)
1756#define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos)
1758#define SYS_GPA_MFPH_PA9MFP_Pos (4)
1759#define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos)
1761#define SYS_GPA_MFPH_PA10MFP_Pos (8)
1762#define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos)
1764#define SYS_GPA_MFPH_PA11MFP_Pos (12)
1765#define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos)
1767#define SYS_GPA_MFPH_PA12MFP_Pos (16)
1768#define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos)
1770#define SYS_GPA_MFPH_PA13MFP_Pos (20)
1771#define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos)
1773#define SYS_GPA_MFPH_PA14MFP_Pos (24)
1774#define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos)
1776#define SYS_GPA_MFPH_PA15MFP_Pos (28)
1777#define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos)
1779#define SYS_GPB_MFPL_PB0MFP_Pos (0)
1780#define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos)
1782#define SYS_GPB_MFPL_PB1MFP_Pos (4)
1783#define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos)
1785#define SYS_GPB_MFPL_PB2MFP_Pos (8)
1786#define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos)
1788#define SYS_GPB_MFPL_PB3MFP_Pos (12)
1789#define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos)
1791#define SYS_GPB_MFPL_PB4MFP_Pos (16)
1792#define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos)
1794#define SYS_GPB_MFPL_PB5MFP_Pos (20)
1795#define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos)
1797#define SYS_GPB_MFPL_PB6MFP_Pos (24)
1798#define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos)
1800#define SYS_GPB_MFPL_PB7MFP_Pos (28)
1801#define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos)
1803#define SYS_GPB_MFPH_PB8MFP_Pos (0)
1804#define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos)
1806#define SYS_GPB_MFPH_PB9MFP_Pos (4)
1807#define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos)
1809#define SYS_GPB_MFPH_PB10MFP_Pos (8)
1810#define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos)
1812#define SYS_GPB_MFPH_PB11MFP_Pos (12)
1813#define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos)
1815#define SYS_GPB_MFPH_PB13MFP_Pos (20)
1816#define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos)
1818#define SYS_GPB_MFPH_PB14MFP_Pos (24)
1819#define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos)
1821#define SYS_GPB_MFPH_PB15MFP_Pos (28)
1822#define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos)
1824#define SYS_GPC_MFPL_PC0MFP_Pos (0)
1825#define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos)
1827#define SYS_GPC_MFPL_PC1MFP_Pos (4)
1828#define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos)
1830#define SYS_GPC_MFPL_PC2MFP_Pos (8)
1831#define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos)
1833#define SYS_GPC_MFPL_PC3MFP_Pos (12)
1834#define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos)
1836#define SYS_GPC_MFPL_PC6MFP_Pos (24)
1837#define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos)
1839#define SYS_GPC_MFPL_PC7MFP_Pos (28)
1840#define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos)
1842#define SYS_GPC_MFPH_PC8MFP_Pos (0)
1843#define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos)
1845#define SYS_GPC_MFPH_PC9MFP_Pos (4)
1846#define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos)
1848#define SYS_GPC_MFPH_PC10MFP_Pos (8)
1849#define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos)
1851#define SYS_GPC_MFPH_PC11MFP_Pos (12)
1852#define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos)
1854#define SYS_GPC_MFPH_PC14MFP_Pos (24)
1855#define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos)
1857#define SYS_GPC_MFPH_PC15MFP_Pos (28)
1858#define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos)
1860#define SYS_GPD_MFPL_PD6MFP_Pos (24)
1861#define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos)
1863#define SYS_GPD_MFPL_PD7MFP_Pos (28)
1864#define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos)
1866#define SYS_GPD_MFPH_PD14MFP_Pos (24)
1867#define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos)
1869#define SYS_GPD_MFPH_PD15MFP_Pos (28)
1870#define SYS_GPD_MFPH_PD15MFP_Msk (0x7ul << SYS_GPD_MFPH_PD15MFP_Pos)
1872#define SYS_GPE_MFPL_PE5MFP_Pos (20)
1873#define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos)
1875#define SYS_GPF_MFPL_PF0MFP_Pos (0)
1876#define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos)
1878#define SYS_GPF_MFPL_PF1MFP_Pos (4)
1879#define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos)
1881#define SYS_GPF_MFPL_PF2MFP_Pos (8)
1882#define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos)
1884#define SYS_GPF_MFPL_PF3MFP_Pos (12)
1885#define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos)
1887#define SYS_GPF_MFPL_PF6MFP_Pos (24)
1888#define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos)
1890#define SYS_GPF_MFPL_PF7MFP_Pos (28)
1891#define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos)
1893#define SYS_PORCTL_POROFF_Pos (0)
1894#define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos)
1896#define SYS_BODCTL_BODEN_Pos (0)
1897#define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos)
1899#define SYS_BODCTL_BODIE_Pos (2)
1900#define SYS_BODCTL_BODIE_Msk (0x1ul << SYS_BODCTL_BODIE_Pos)
1902#define SYS_BODCTL_BODREN_Pos (3)
1903#define SYS_BODCTL_BODREN_Msk (0x1ul << SYS_BODCTL_BODREN_Pos)
1905#define SYS_BODCTL_BODIF_Pos (4)
1906#define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos)
1908#define SYS_BODCTL_BODOUT_Pos (6)
1909#define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos)
1911#define SYS_BODCTL_LVREN_Pos (7)
1912#define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos)
1914#define SYS_BODCTL_LPBODEN_Pos (8)
1915#define SYS_BODCTL_LPBODEN_Msk (0x1ul << SYS_BODCTL_LPBODEN_Pos)
1917#define SYS_BODCTL_LPBODVL_Pos (9)
1918#define SYS_BODCTL_LPBODVL_Msk (0x1ul << SYS_BODCTL_LPBODVL_Pos)
1920#define SYS_BODCTL_LPBODIE_Pos (10)
1921#define SYS_BODCTL_LPBODIE_Msk (0x1ul << SYS_BODCTL_LPBODIE_Pos)
1923#define SYS_BODCTL_LPBODREN_Pos (11)
1924#define SYS_BODCTL_LPBODREN_Msk (0x1ul << SYS_BODCTL_LPBODREN_Pos)
1926#define SYS_BODCTL_BODVL_Pos (12)
1927#define SYS_BODCTL_BODVL_Msk (0xful << SYS_BODCTL_BODVL_Pos)
1929#define SYS_BODCTL_LPBOD20TRIM_Pos (16)
1930#define SYS_BODCTL_LPBOD20TRIM_Msk (0xful << SYS_BODCTL_LPBOD20TRIM_Pos)
1932#define SYS_BODCTL_LPBOD25TRIM_Pos (20)
1933#define SYS_BODCTL_LPBOD25TRIM_Msk (0xful << SYS_BODCTL_LPBOD25TRIM_Pos)
1935#define SYS_BODCTL_BODDGSEL_Pos (24)
1936#define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos)
1938#define SYS_BODCTL_LVRDGSEL_Pos (28)
1939#define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos)
1941#define SYS_IVREFCTL_BGPEN_Pos (0)
1942#define SYS_IVREFCTL_BGPEN_Msk (0x1ul << SYS_IVREFCTL_BGPEN_Pos)
1944#define SYS_IVREFCTL_REGEN_Pos (1)
1945#define SYS_IVREFCTL_REGEN_Msk (0x1ul << SYS_IVREFCTL_REGEN_Pos)
1947#define SYS_IVREFCTL_SEL25_Pos (2)
1948#define SYS_IVREFCTL_SEL25_Msk (0x3ul << SYS_IVREFCTL_SEL25_Pos)
1950#define SYS_IVREFCTL_EXTMODE_Pos (4)
1951#define SYS_IVREFCTL_EXTMODE_Msk (0x1ul << SYS_IVREFCTL_EXTMODE_Pos)
1953#define SYS_IVREFCTL_VREFTRIM_Pos (8)
1954#define SYS_IVREFCTL_VREFTRIM_Msk (0xful << SYS_IVREFCTL_VREFTRIM_Pos)
1956#define SYS_LDOCTL_FASTWK_Pos (1)
1957#define SYS_LDOCTL_FASTWK_Msk (0x1ul << SYS_LDOCTL_FASTWK_Pos)
1959#define SYS_LDOCTL_LDOLVL_Pos (2)
1960#define SYS_LDOCTL_LDOLVL_Msk (0x3ul << SYS_LDOCTL_LDOLVL_Pos)
1962#define SYS_LDOCTL_LPRMEN_Pos (4)
1963#define SYS_LDOCTL_LPRMEN_Msk (0x1ul << SYS_LDOCTL_LPRMEN_Pos)
1965#define SYS_LDOCTL_FMCLVEN_Pos (5)
1966#define SYS_LDOCTL_FMCLVEN_Msk (0x1ul << SYS_LDOCTL_FMCLVEN_Pos)
1968#define SYS_BATDIVCTL_BATDIV2EN_Pos (0)
1969#define SYS_BATDIVCTL_BATDIV2EN_Msk (0x1ul << SYS_BATDIVCTL_BATDIV2EN_Pos)
1971#define SYS_WKSTS_ACMPWK_Pos (0)
1972#define SYS_WKSTS_ACMPWK_Msk (0x1ul << SYS_WKSTS_ACMPWK_Pos)
1974#define SYS_WKSTS_I2C1WK_Pos (1)
1975#define SYS_WKSTS_I2C1WK_Msk (0x1ul << SYS_WKSTS_I2C1WK_Pos)
1977#define SYS_WKSTS_I2C0WK_Pos (2)
1978#define SYS_WKSTS_I2C0WK_Msk (0x1ul << SYS_WKSTS_I2C0WK_Pos)
1980#define SYS_WKSTS_TMR3WK_Pos (3)
1981#define SYS_WKSTS_TMR3WK_Msk (0x1ul << SYS_WKSTS_TMR3WK_Pos)
1983#define SYS_WKSTS_TMR2WK_Pos (4)
1984#define SYS_WKSTS_TMR2WK_Msk (0x1ul << SYS_WKSTS_TMR2WK_Pos)
1986#define SYS_WKSTS_TMR1WK_Pos (5)
1987#define SYS_WKSTS_TMR1WK_Msk (0x1ul << SYS_WKSTS_TMR1WK_Pos)
1989#define SYS_WKSTS_TMR0WK_Pos (6)
1990#define SYS_WKSTS_TMR0WK_Msk (0x1ul << SYS_WKSTS_TMR0WK_Pos)
1992#define SYS_WKSTS_WDTWK_Pos (7)
1993#define SYS_WKSTS_WDTWK_Msk (0x1ul << SYS_WKSTS_WDTWK_Pos)
1995#define SYS_WKSTS_BODWK_Pos (8)
1996#define SYS_WKSTS_BODWK_Msk (0x1ul << SYS_WKSTS_BODWK_Pos)
1998#define SYS_WKSTS_SPI3WK_Pos (9)
1999#define SYS_WKSTS_SPI3WK_Msk (0x1ul << SYS_WKSTS_SPI3WK_Pos)
2001#define SYS_WKSTS_SPI2WK_Pos (10)
2002#define SYS_WKSTS_SPI2WK_Msk (0x1ul << SYS_WKSTS_SPI2WK_Pos)
2004#define SYS_WKSTS_SPI1WK_Pos (11)
2005#define SYS_WKSTS_SPI1WK_Msk (0x1ul << SYS_WKSTS_SPI1WK_Pos)
2007#define SYS_WKSTS_SPI0WK_Pos (12)
2008#define SYS_WKSTS_SPI0WK_Msk (0x1ul << SYS_WKSTS_SPI0WK_Pos)
2010#define SYS_WKSTS_UART1WK_Pos (13)
2011#define SYS_WKSTS_UART1WK_Msk (0x1ul << SYS_WKSTS_UART1WK_Pos)
2013#define SYS_WKSTS_UART0WK_Pos (14)
2014#define SYS_WKSTS_UART0WK_Msk (0x1ul << SYS_WKSTS_UART0WK_Pos)
2016#define SYS_WKSTS_RTCWK_Pos (15)
2017#define SYS_WKSTS_RTCWK_Msk (0x1ul << SYS_WKSTS_RTCWK_Pos)
2019#define SYS_WKSTS_GPIOWK_Pos (16)
2020#define SYS_WKSTS_GPIOWK_Msk (0x1ul << SYS_WKSTS_GPIOWK_Pos)
2022#define SYS_IRC0TCTL_FREQSEL_Pos (0)
2023#define SYS_IRC0TCTL_FREQSEL_Msk (0x7ul << SYS_IRC0TCTL_FREQSEL_Pos)
2025#define SYS_IRC0TCTL_LOOPSEL_Pos (4)
2026#define SYS_IRC0TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC0TCTL_LOOPSEL_Pos)
2028#define SYS_IRC0TCTL_RETRYCNT_Pos (6)
2029#define SYS_IRC0TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC0TCTL_RETRYCNT_Pos)
2031#define SYS_IRC0TCTL_CESTOPEN_Pos (8)
2032#define SYS_IRC0TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC0TCTL_CESTOPEN_Pos)
2034#define SYS_IRC0TIEN_TFAILIEN_Pos (1)
2035#define SYS_IRC0TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC0TIEN_TFAILIEN_Pos)
2037#define SYS_IRC0TIEN_CLKEIEN_Pos (2)
2038#define SYS_IRC0TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC0TIEN_CLKEIEN_Pos)
2040#define SYS_IRC0TISTS_FREQLOCK_Pos (0)
2041#define SYS_IRC0TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC0TISTS_FREQLOCK_Pos)
2043#define SYS_IRC0TISTS_TFAILIF_Pos (1)
2044#define SYS_IRC0TISTS_TFAILIF_Msk (0x1ul << SYS_IRC0TISTS_TFAILIF_Pos)
2046#define SYS_IRC0TISTS_CLKERRIF_Pos (2)
2047#define SYS_IRC0TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC0TISTS_CLKERRIF_Pos)
2049#define SYS_IRC1TCTL_FREQSEL_Pos (0)
2050#define SYS_IRC1TCTL_FREQSEL_Msk (0x3ul << SYS_IRC1TCTL_FREQSEL_Pos)
2052#define SYS_IRC1TCTL_LOOPSEL_Pos (4)
2053#define SYS_IRC1TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC1TCTL_LOOPSEL_Pos)
2055#define SYS_IRC1TCTL_RETRYCNT_Pos (6)
2056#define SYS_IRC1TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC1TCTL_RETRYCNT_Pos)
2058#define SYS_IRC1TCTL_CESTOPEN_Pos (8)
2059#define SYS_IRC1TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC1TCTL_CESTOPEN_Pos)
2061#define SYS_IRC1TIEN_TFAILIEN_Pos (1)
2062#define SYS_IRC1TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC1TIEN_TFAILIEN_Pos)
2064#define SYS_IRC1TIEN_CLKEIEN_Pos (2)
2065#define SYS_IRC1TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC1TIEN_CLKEIEN_Pos)
2067#define SYS_IRC1TISTS_FREQLOCK_Pos (0)
2068#define SYS_IRC1TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC1TISTS_FREQLOCK_Pos)
2070#define SYS_IRC1TISTS_TFAILIF_Pos (1)
2071#define SYS_IRC1TISTS_TFAILIF_Msk (0x1ul << SYS_IRC1TISTS_TFAILIF_Pos)
2073#define SYS_IRC1TISTS_CLKERRIF_Pos (2)
2074#define SYS_IRC1TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC1TISTS_CLKERRIF_Pos)
2076#define SYS_MIRCTCTL_FREQSEL_Pos (0)
2077#define SYS_MIRCTCTL_FREQSEL_Msk (0x3ul << SYS_MIRCTCTL_FREQSEL_Pos)
2079#define SYS_MIRCTCTL_LOOPSEL_Pos (4)
2080#define SYS_MIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_MIRCTCTL_LOOPSEL_Pos)
2082#define SYS_MIRCTCTL_RETRYCNT_Pos (6)
2083#define SYS_MIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_MIRCTCTL_RETRYCNT_Pos)
2085#define SYS_MIRCTCTL_CESTOPEN_Pos (8)
2086#define SYS_MIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_MIRCTCTL_CESTOPEN_Pos)
2088#define SYS_MIRCTIEN_TFAILIEN_Pos (1)
2089#define SYS_MIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_MIRCTIEN_TFAILIEN_Pos)
2091#define SYS_MIRCTIEN_CLKEIEN_Pos (2)
2092#define SYS_MIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_MIRCTIEN_CLKEIEN_Pos)
2094#define SYS_MIRCTISTS_FREQLOCK_Pos (0)
2095#define SYS_MIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_MIRCTISTS_FREQLOCK_Pos)
2097#define SYS_MIRCTISTS_TFAILIF_Pos (1)
2098#define SYS_MIRCTISTS_TFAILIF_Msk (0x1ul << SYS_MIRCTISTS_TFAILIF_Pos)
2100#define SYS_MIRCTISTS_CLKERRIF_Pos (2)
2101#define SYS_MIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_MIRCTISTS_CLKERRIF_Pos)
2103#define SYS_REGLCTL_REGLCTL_Pos (0)
2104#define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos)
2106#define SYS_RPDBCLK_RSTPDBCLK_Pos (6)
2107#define SYS_RPDBCLK_RSTPDBCLK_Msk (0x1ul << SYS_RPDBCLK_RSTPDBCLK_Pos) /* SYS_CONST */ /* end of SYS register group */
2111
2112
2113/*---------------------- System Clock Controller -------------------------*/
2119typedef struct
2120{
2121
2122
2626 __IO uint32_t PWRCTL;
2627 __IO uint32_t AHBCLK;
2628 __IO uint32_t APBCLK;
2629 __I uint32_t STATUS;
2630 __IO uint32_t CLKSEL0;
2631 __IO uint32_t CLKSEL1;
2632 __IO uint32_t CLKSEL2;
2633 __IO uint32_t CLKDIV0;
2634 __IO uint32_t CLKDIV1;
2635 __IO uint32_t PLLCTL;
2636 __IO uint32_t CLKOCTL;
2638 __I uint32_t RESERVE0[1];
2640 __IO uint32_t WKINTSTS;
2641 __IO uint32_t APBDIV;
2642 __IO uint32_t CLKDCTL;
2643 __IO uint32_t CLKDIE;
2644 __IO uint32_t CLKDSTS;
2645 __IO uint32_t CDUPB;
2646 __IO uint32_t CDLOWB;
2647} CLK_T;
2648
2654#define CLK_PWRCTL_HXTEN_Pos (0)
2655#define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos)
2657#define CLK_PWRCTL_LXTEN_Pos (1)
2658#define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos)
2660#define CLK_PWRCTL_HIRC0EN_Pos (2)
2661#define CLK_PWRCTL_HIRC0EN_Msk (0x1ul << CLK_PWRCTL_HIRC0EN_Pos)
2663#define CLK_PWRCTL_LIRCEN_Pos (3)
2664#define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos)
2666#define CLK_PWRCTL_PDWKDLY_Pos (4)
2667#define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos)
2669#define CLK_PWRCTL_PDWKIEN_Pos (5)
2670#define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos)
2672#define CLK_PWRCTL_PDEN_Pos (6)
2673#define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos)
2675#define CLK_PWRCTL_HXTSLTYP_Pos (8)
2676#define CLK_PWRCTL_HXTSLTYP_Msk (0x1ul << CLK_PWRCTL_HXTSLTYP_Pos)
2678#define CLK_PWRCTL_HXTGAIN_Pos (10)
2679#define CLK_PWRCTL_HXTGAIN_Msk (0x7ul << CLK_PWRCTL_HXTGAIN_Pos)
2681#define CLK_PWRCTL_HIRC0FSEL_Pos (13)
2682#define CLK_PWRCTL_HIRC0FSEL_Msk (0x1ul << CLK_PWRCTL_HIRC0FSEL_Pos)
2684#define CLK_PWRCTL_HIRC0FSTOP_Pos (14)
2685#define CLK_PWRCTL_HIRC0FSTOP_Msk (0x1ul << CLK_PWRCTL_HIRC0FSTOP_Pos)
2687#define CLK_PWRCTL_HIRC1EN_Pos (24)
2688#define CLK_PWRCTL_HIRC1EN_Msk (0x1ul << CLK_PWRCTL_HIRC1EN_Pos)
2690#define CLK_PWRCTL_MIRCEN_Pos (25)
2691#define CLK_PWRCTL_MIRCEN_Msk (0x1ul << CLK_PWRCTL_MIRCEN_Pos)
2693#define CLK_AHBCLK_GPIOCKEN_Pos (0)
2694#define CLK_AHBCLK_GPIOCKEN_Msk (0x1ul << CLK_AHBCLK_GPIOCKEN_Pos)
2696#define CLK_AHBCLK_PDMACKEN_Pos (1)
2697#define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos)
2699#define CLK_AHBCLK_ISPCKEN_Pos (2)
2700#define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos)
2702#define CLK_AHBCLK_SRAMCKEN_Pos (4)
2703#define CLK_AHBCLK_SRAMCKEN_Msk (0x1ul << CLK_AHBCLK_SRAMCKEN_Pos)
2705#define CLK_AHBCLK_STCKEN_Pos (5)
2706#define CLK_AHBCLK_STCKEN_Msk (0x1ul << CLK_AHBCLK_STCKEN_Pos)
2708#define CLK_APBCLK_WDTCKEN_Pos (0)
2709#define CLK_APBCLK_WDTCKEN_Msk (0x1ul << CLK_APBCLK_WDTCKEN_Pos)
2711#define CLK_APBCLK_RTCCKEN_Pos (1)
2712#define CLK_APBCLK_RTCCKEN_Msk (0x1ul << CLK_APBCLK_RTCCKEN_Pos)
2714#define CLK_APBCLK_TMR0CKEN_Pos (2)
2715#define CLK_APBCLK_TMR0CKEN_Msk (0x1ul << CLK_APBCLK_TMR0CKEN_Pos)
2717#define CLK_APBCLK_TMR1CKEN_Pos (3)
2718#define CLK_APBCLK_TMR1CKEN_Msk (0x1ul << CLK_APBCLK_TMR1CKEN_Pos)
2720#define CLK_APBCLK_TMR2CKEN_Pos (4)
2721#define CLK_APBCLK_TMR2CKEN_Msk (0x1ul << CLK_APBCLK_TMR2CKEN_Pos)
2723#define CLK_APBCLK_TMR3CKEN_Pos (5)
2724#define CLK_APBCLK_TMR3CKEN_Msk (0x1ul << CLK_APBCLK_TMR3CKEN_Pos)
2726#define CLK_APBCLK_CLKOCKEN_Pos (6)
2727#define CLK_APBCLK_CLKOCKEN_Msk (0x1ul << CLK_APBCLK_CLKOCKEN_Pos)
2729#define CLK_APBCLK_I2C0CKEN_Pos (8)
2730#define CLK_APBCLK_I2C0CKEN_Msk (0x1ul << CLK_APBCLK_I2C0CKEN_Pos)
2732#define CLK_APBCLK_I2C1CKEN_Pos (9)
2733#define CLK_APBCLK_I2C1CKEN_Msk (0x1ul << CLK_APBCLK_I2C1CKEN_Pos)
2735#define CLK_APBCLK_ACMP0CKEN_Pos (11)
2736#define CLK_APBCLK_ACMP0CKEN_Msk (0x1ul << CLK_APBCLK_ACMP0CKEN_Pos)
2738#define CLK_APBCLK_SPI0CKEN_Pos (12)
2739#define CLK_APBCLK_SPI0CKEN_Msk (0x1ul << CLK_APBCLK_SPI0CKEN_Pos)
2741#define CLK_APBCLK_SPI1CKEN_Pos (13)
2742#define CLK_APBCLK_SPI1CKEN_Msk (0x1ul << CLK_APBCLK_SPI1CKEN_Pos)
2744#define CLK_APBCLK_SPI2CKEN_Pos (14)
2745#define CLK_APBCLK_SPI2CKEN_Msk (0x1ul << CLK_APBCLK_SPI2CKEN_Pos)
2747#define CLK_APBCLK_SPI3CKEN_Pos (15)
2748#define CLK_APBCLK_SPI3CKEN_Msk (0x1ul << CLK_APBCLK_SPI3CKEN_Pos)
2750#define CLK_APBCLK_UART0CKEN_Pos (16)
2751#define CLK_APBCLK_UART0CKEN_Msk (0x1ul << CLK_APBCLK_UART0CKEN_Pos)
2753#define CLK_APBCLK_UART1CKEN_Pos (17)
2754#define CLK_APBCLK_UART1CKEN_Msk (0x1ul << CLK_APBCLK_UART1CKEN_Pos)
2756#define CLK_APBCLK_PWM0CKEN_Pos (20)
2757#define CLK_APBCLK_PWM0CKEN_Msk (0x1ul << CLK_APBCLK_PWM0CKEN_Pos)
2759#define CLK_APBCLK_ADCCKEN_Pos (28)
2760#define CLK_APBCLK_ADCCKEN_Msk (0x1ul << CLK_APBCLK_ADCCKEN_Pos)
2762#define CLK_APBCLK_SC0CKEN_Pos (30)
2763#define CLK_APBCLK_SC0CKEN_Msk (0x1ul << CLK_APBCLK_SC0CKEN_Pos)
2765#define CLK_APBCLK_SC1CKEN_Pos (31)
2766#define CLK_APBCLK_SC1CKEN_Msk (0x1ul << CLK_APBCLK_SC1CKEN_Pos)
2768#define CLK_STATUS_HXTSTB_Pos (0)
2769#define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos)
2771#define CLK_STATUS_LXTSTB_Pos (1)
2772#define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos)
2774#define CLK_STATUS_PLLSTB_Pos (2)
2775#define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos)
2777#define CLK_STATUS_LIRCSTB_Pos (3)
2778#define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos)
2780#define CLK_STATUS_HIRC0STB_Pos (4)
2781#define CLK_STATUS_HIRC0STB_Msk (0x1ul << CLK_STATUS_HIRC0STB_Pos)
2783#define CLK_STATUS_HIRC1STB_Pos (5)
2784#define CLK_STATUS_HIRC1STB_Msk (0x1ul << CLK_STATUS_HIRC1STB_Pos)
2786#define CLK_STATUS_MIRCSTB_Pos (6)
2787#define CLK_STATUS_MIRCSTB_Msk (0x1ul << CLK_STATUS_MIRCSTB_Pos)
2789#define CLK_STATUS_CLKSFAIL_Pos (7)
2790#define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos)
2792#define CLK_CLKSEL0_HCLKSEL_Pos (0)
2793#define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos)
2795#define CLK_CLKSEL0_HIRCSEL_Pos (3)
2796#define CLK_CLKSEL0_HIRCSEL_Msk (0x1ul << CLK_CLKSEL0_HIRCSEL_Pos)
2798#define CLK_CLKSEL0_ISPSEL_Pos (4)
2799#define CLK_CLKSEL0_ISPSEL_Msk (0x1ul << CLK_CLKSEL0_ISPSEL_Pos)
2801#define CLK_CLKSEL1_UART0SEL_Pos (0)
2802#define CLK_CLKSEL1_UART0SEL_Msk (0x7ul << CLK_CLKSEL1_UART0SEL_Pos)
2804#define CLK_CLKSEL1_PWM0SEL_Pos (4)
2805#define CLK_CLKSEL1_PWM0SEL_Msk (0x1ul << CLK_CLKSEL1_PWM0SEL_Pos)
2807#define CLK_CLKSEL1_TMR0SEL_Pos (8)
2808#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos)
2810#define CLK_CLKSEL1_TMR1SEL_Pos (12)
2811#define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos)
2813#define CLK_CLKSEL1_ADCSEL_Pos (19)
2814#define CLK_CLKSEL1_ADCSEL_Msk (0x7ul << CLK_CLKSEL1_ADCSEL_Pos)
2816#define CLK_CLKSEL1_SPI0SEL_Pos (24)
2817#define CLK_CLKSEL1_SPI0SEL_Msk (0x3ul << CLK_CLKSEL1_SPI0SEL_Pos)
2819#define CLK_CLKSEL1_SPI2SEL_Pos (26)
2820#define CLK_CLKSEL1_SPI2SEL_Msk (0x3ul << CLK_CLKSEL1_SPI2SEL_Pos)
2822#define CLK_CLKSEL1_WDTSEL_Pos (28)
2823#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos)
2825#define CLK_CLKSEL1_WWDTSEL_Pos (30)
2826#define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos)
2828#define CLK_CLKSEL2_UART1SEL_Pos (0)
2829#define CLK_CLKSEL2_UART1SEL_Msk (0x7ul << CLK_CLKSEL2_UART1SEL_Pos)
2831#define CLK_CLKSEL2_CLKOSEL_Pos (4)
2832#define CLK_CLKSEL2_CLKOSEL_Msk (0x7ul << CLK_CLKSEL2_CLKOSEL_Pos)
2834#define CLK_CLKSEL2_TMR2SEL_Pos (8)
2835#define CLK_CLKSEL2_TMR2SEL_Msk (0x7ul << CLK_CLKSEL2_TMR2SEL_Pos)
2837#define CLK_CLKSEL2_TMR3SEL_Pos (12)
2838#define CLK_CLKSEL2_TMR3SEL_Msk (0x7ul << CLK_CLKSEL2_TMR3SEL_Pos)
2840#define CLK_CLKSEL2_SC0SEL_Pos (16)
2841#define CLK_CLKSEL2_SC0SEL_Msk (0x7ul << CLK_CLKSEL2_SC0SEL_Pos)
2843#define CLK_CLKSEL2_SC1SEL_Pos (20)
2844#define CLK_CLKSEL2_SC1SEL_Msk (0x7ul << CLK_CLKSEL2_SC1SEL_Pos)
2846#define CLK_CLKSEL2_SPI1SEL_Pos (24)
2847#define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos)
2849#define CLK_CLKSEL2_SPI3SEL_Pos (26)
2850#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos)
2852#define CLK_CLKDIV0_HCLKDIV_Pos (0)
2853#define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos)
2855#define CLK_CLKDIV0_UART0DIV_Pos (8)
2856#define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos)
2858#define CLK_CLKDIV0_UART1DIV_Pos (12)
2859#define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos)
2861#define CLK_CLKDIV0_ADCDIV_Pos (16)
2862#define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos)
2864#define CLK_CLKDIV0_SC0DIV_Pos (28)
2865#define CLK_CLKDIV0_SC0DIV_Msk (0xful << CLK_CLKDIV0_SC0DIV_Pos)
2867#define CLK_CLKDIV1_SC1DIV_Pos (0)
2868#define CLK_CLKDIV1_SC1DIV_Msk (0xful << CLK_CLKDIV1_SC1DIV_Pos)
2870#define CLK_CLKDIV1_TMR0DIV_Pos (8)
2871#define CLK_CLKDIV1_TMR0DIV_Msk (0xful << CLK_CLKDIV1_TMR0DIV_Pos)
2873#define CLK_CLKDIV1_TMR1DIV_Pos (12)
2874#define CLK_CLKDIV1_TMR1DIV_Msk (0xful << CLK_CLKDIV1_TMR1DIV_Pos)
2876#define CLK_CLKDIV1_TMR2DIV_Pos (16)
2877#define CLK_CLKDIV1_TMR2DIV_Msk (0xful << CLK_CLKDIV1_TMR2DIV_Pos)
2879#define CLK_CLKDIV1_TMR3DIV_Pos (20)
2880#define CLK_CLKDIV1_TMR3DIV_Msk (0xful << CLK_CLKDIV1_TMR3DIV_Pos)
2882#define CLK_PLLCTL_PLLMLP_Pos (0)
2883#define CLK_PLLCTL_PLLMLP_Msk (0x3ful << CLK_PLLCTL_PLLMLP_Pos)
2885#define CLK_PLLCTL_INDIV_Pos (8)
2886#define CLK_PLLCTL_INDIV_Msk (0x3ful << CLK_PLLCTL_INDIV_Pos)
2888#define CLK_PLLCTL_STBTSEL_Pos (14)
2889#define CLK_PLLCTL_STBTSEL_Msk (0x3ul << CLK_PLLCTL_STBTSEL_Pos)
2891#define CLK_PLLCTL_PD_Pos (16)
2892#define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos)
2894#define CLK_PLLCTL_PLLSRC_Pos (17)
2895#define CLK_PLLCTL_PLLSRC_Msk (0x3ul << CLK_PLLCTL_PLLSRC_Pos)
2897#define CLK_CLKOCTL_FREQSEL_Pos (0)
2898#define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos)
2900#define CLK_CLKOCTL_CLKOEN_Pos (4)
2901#define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos)
2903#define CLK_CLKOCTL_DIV1EN_Pos (5)
2904#define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos)
2906#define CLK_WKINTSTS_PDWKIF_Pos (0)
2907#define CLK_WKINTSTS_PDWKIF_Msk (0x1ul << CLK_WKINTSTS_PDWKIF_Pos)
2909#define CLK_APBDIV_APB0DIV_Pos (0)
2910#define CLK_APBDIV_APB0DIV_Msk (0x7ul << CLK_APBDIV_APB0DIV_Pos)
2912#define CLK_APBDIV_APB1DIV_Pos (4)
2913#define CLK_APBDIV_APB1DIV_Msk (0x7ul << CLK_APBDIV_APB1DIV_Pos)
2915#define CLK_CLKDCTL_HXTFDEN_Pos (0)
2916#define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos)
2918#define CLK_CLKDCTL_LXTFDEN_Pos (1)
2919#define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos)
2921#define CLK_CLKDCTL_HXTFQDEN_Pos (2)
2922#define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos)
2924#define CLK_CLKDIE_HXTFIEN_Pos (0)
2925#define CLK_CLKDIE_HXTFIEN_Msk (0x1ul << CLK_CLKDIE_HXTFIEN_Pos)
2927#define CLK_CLKDIE_LXTFIEN_Pos (1)
2928#define CLK_CLKDIE_LXTFIEN_Msk (0x1ul << CLK_CLKDIE_LXTFIEN_Pos)
2930#define CLK_CLKDIE_HXTFQIEN_Pos (2)
2931#define CLK_CLKDIE_HXTFQIEN_Msk (0x1ul << CLK_CLKDIE_HXTFQIEN_Pos)
2933#define CLK_CLKDSTS_HXTFIF_Pos (0)
2934#define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos)
2936#define CLK_CLKDSTS_LXTFIF_Pos (1)
2937#define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos)
2939#define CLK_CLKDSTS_HXTFQIF_Pos (2)
2940#define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos)
2942#define CLK_CDUPB_UPERBD_Pos (0)
2943#define CLK_CDUPB_UPERBD_Msk (0x7fful << CLK_CDUPB_UPERBD_Pos)
2945#define CLK_CDLOWB_LOWERBD_Pos (0)
2946#define CLK_CDLOWB_LOWERBD_Msk (0x7fful << CLK_CDLOWB_LOWERBD_Pos) /* CLK_CONST */ /* end of CLK register group */
2950
2951
2952/*---------------------- Flash Memory Controller -------------------------*/
2958typedef struct
2959{
2960
2961
3233 __IO uint32_t ISPCTL;
3234 __IO uint32_t ISPADDR;
3235 __IO uint32_t ISPDAT;
3236 __IO uint32_t ISPCMD;
3237 __IO uint32_t ISPTRG;
3238 __I uint32_t DFBA;
3239 __IO uint32_t FTCTL;
3241 __I uint32_t RESERVE0[9];
3243 __IO uint32_t ISPSTS;
3245 __I uint32_t RESERVE1[3];
3247 __O uint32_t KEY0;
3248 __O uint32_t KEY1;
3249 __O uint32_t KEY2;
3250 __IO uint32_t KEYTRG;
3251 __IO uint32_t KEYSTS;
3252 __I uint32_t KECNT;
3253 __I uint32_t KPCNT;
3255} FMC_T;
3256
3262#define FMC_ISPCTL_ISPEN_Pos (0)
3263#define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos)
3265#define FMC_ISPCTL_BS_Pos (1)
3266#define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos)
3268#define FMC_ISPCTL_APUEN_Pos (3)
3269#define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos)
3271#define FMC_ISPCTL_CFGUEN_Pos (4)
3272#define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos)
3274#define FMC_ISPCTL_LDUEN_Pos (5)
3275#define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos)
3277#define FMC_ISPCTL_ISPFF_Pos (6)
3278#define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos)
3280#define FMC_ISPADDR_ISPADDR_Pos (0)
3281#define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos)
3283#define FMC_ISPDAT_ISPDAT_Pos (0)
3284#define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos)
3286#define FMC_ISPCMD_CMD_Pos (0)
3287#define FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos)
3289#define FMC_ISPTRG_ISPGO_Pos (0)
3290#define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos)
3292#define FMC_DFBA_DFBA_Pos (0)
3293#define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos)
3295#define FMC_FTCTL_FOM_Pos (4)
3296#define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos)
3298#define FMC_FTCTL_CACHEOFF_Pos (7)
3299#define FMC_FTCTL_CACHEOFF_Msk (0x1ul << FMC_FTCTL_CACHEOFF_Pos)
3301#define FMC_ISPSTS_ISPBUSY_Pos (0)
3302#define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos)
3304#define FMC_ISPSTS_CBS_Pos (1)
3305#define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos)
3307#define FMC_ISPSTS_PGFF_Pos (5)
3308#define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos)
3310#define FMC_ISPSTS_ISPFF_Pos (6)
3311#define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos)
3313#define FMC_ISPSTS_ALLONE_Pos (7)
3314#define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos)
3316#define FMC_ISPSTS_VECMAP_Pos (9)
3317#define FMC_ISPSTS_VECMAP_Msk (0x1ffffful << FMC_ISPSTS_VECMAP_Pos)
3319#define FMC_KEY0_KEY0_Pos (0)
3320#define FMC_KEY0_KEY0_Msk (0xfffffffful << FMC_KEY0_KEY0_Pos)
3322#define FMC_KEY1_KEY1_Pos (0)
3323#define FMC_KEY1_KEY1_Msk (0xfffffffful << FMC_KEY1_KEY1_Pos)
3325#define FMC_KEY2_KEY2_Pos (0)
3326#define FMC_KEY2_KEY2_Msk (0xfffffffful << FMC_KEY2_KEY2_Pos)
3328#define FMC_KEYTRG_KEYGO_Pos (0)
3329#define FMC_KEYTRG_KEYGO_Msk (0x1ul << FMC_KEYTRG_KEYGO_Pos)
3331#define FMC_KEYTRG_TCEN_Pos (1)
3332#define FMC_KEYTRG_TCEN_Msk (0x1ul << FMC_KEYTRG_TCEN_Pos)
3334#define FMC_KEYSTS_KEYBUSY_Pos (0)
3335#define FMC_KEYSTS_KEYBUSY_Msk (0x1ul << FMC_KEYSTS_KEYBUSY_Pos)
3337#define FMC_KEYSTS_KEYLOCK_Pos (1)
3338#define FMC_KEYSTS_KEYLOCK_Msk (0x1ul << FMC_KEYSTS_KEYLOCK_Pos)
3340#define FMC_KEYSTS_KEYMATCH_Pos (2)
3341#define FMC_KEYSTS_KEYMATCH_Msk (0x1ul << FMC_KEYSTS_KEYMATCH_Pos)
3343#define FMC_KEYSTS_FORBID_Pos (3)
3344#define FMC_KEYSTS_FORBID_Msk (0x1ul << FMC_KEYSTS_FORBID_Pos)
3346#define FMC_KEYSTS_KEYFLAG_Pos (4)
3347#define FMC_KEYSTS_KEYFLAG_Msk (0x1ul << FMC_KEYSTS_KEYFLAG_Pos)
3349#define FMC_KEYSTS_CFGFLAG_Pos (5)
3350#define FMC_KEYSTS_CFGFLAG_Msk (0x1ul << FMC_KEYSTS_CFGFLAG_Pos)
3352#define FMC_KECNT_KECNT_Pos (0)
3353#define FMC_KECNT_KECNT_Msk (0x3ful << FMC_KECNT_KECNT_Pos)
3355#define FMC_KECNT_KEMAX_Pos (8)
3356#define FMC_KECNT_KEMAX_Msk (0x3ful << FMC_KECNT_KEMAX_Pos)
3358#define FMC_KPCNT_KPCNT_Pos (0)
3359#define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos)
3361#define FMC_KPCNT_KPMAX_Pos (8)
3362#define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) /* FMC_CONST */ /* end of FMC register group */
3366
3367
3368/*---------------------- General Purpose Input/Output Controller -------------------------*/
3374typedef struct
3375{
3376
3377
6139 __IO uint32_t MODE;
6140 __IO uint32_t DINOFF;
6141 __IO uint32_t DOUT;
6142 __IO uint32_t DATMSK;
6143 __I uint32_t PIN;
6144 __IO uint32_t DBEN;
6145 __IO uint32_t INTTYPE;
6146 __IO uint32_t INTEN;
6147 __IO uint32_t INTSRC;
6148 __IO uint32_t PUEN;
6149 __I uint32_t INTSTS;
6151} GPIO_T;
6152
6153typedef struct
6154{
6155
6187 __IO uint32_t DBCTL;
6188} GP_DB_T;
6189
6195#define GPIO_MODE_MODE0_Pos (0)
6196#define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos)
6198#define GPIO_MODE_MODE1_Pos (2)
6199#define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos)
6201#define GPIO_MODE_MODE2_Pos (4)
6202#define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos)
6204#define GPIO_MODE_MODE3_Pos (6)
6205#define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos)
6207#define GPIO_MODE_MODE4_Pos (8)
6208#define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos)
6210#define GPIO_MODE_MODE5_Pos (10)
6211#define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos)
6213#define GPIO_MODE_MODE6_Pos (12)
6214#define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos)
6216#define GPIO_MODE_MODE7_Pos (14)
6217#define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos)
6219#define GPIO_MODE_MODE8_Pos (16)
6220#define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos)
6222#define GPIO_MODE_MODE9_Pos (18)
6223#define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos)
6225#define GPIO_MODE_MODE10_Pos (20)
6226#define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos)
6228#define GPIO_MODE_MODE11_Pos (22)
6229#define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos)
6231#define GPIO_MODE_MODE12_Pos (24)
6232#define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos)
6234#define GPIO_MODE_MODE13_Pos (26)
6235#define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos)
6237#define GPIO_MODE_MODE14_Pos (28)
6238#define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos)
6240#define GPIO_MODE_MODE15_Pos (30)
6241#define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos)
6243#define GPIO_DINOFF_DINOFF0_Pos (16)
6244#define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos)
6246#define GPIO_DINOFF_DINOFF1_Pos (17)
6247#define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos)
6249#define GPIO_DINOFF_DINOFF2_Pos (18)
6250#define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos)
6252#define GPIO_DINOFF_DINOFF3_Pos (19)
6253#define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos)
6255#define GPIO_DINOFF_DINOFF4_Pos (20)
6256#define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos)
6258#define GPIO_DINOFF_DINOFF5_Pos (21)
6259#define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos)
6261#define GPIO_DINOFF_DINOFF6_Pos (22)
6262#define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos)
6264#define GPIO_DINOFF_DINOFF7_Pos (23)
6265#define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos)
6267#define GPIO_DINOFF_DINOFF8_Pos (24)
6268#define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos)
6270#define GPIO_DINOFF_DINOFF9_Pos (25)
6271#define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos)
6273#define GPIO_DINOFF_DINOFF10_Pos (26)
6274#define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos)
6276#define GPIO_DINOFF_DINOFF11_Pos (27)
6277#define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos)
6279#define GPIO_DINOFF_DINOFF12_Pos (28)
6280#define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos)
6282#define GPIO_DINOFF_DINOFF13_Pos (29)
6283#define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos)
6285#define GPIO_DINOFF_DINOFF14_Pos (30)
6286#define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos)
6288#define GPIO_DINOFF_DINOFF15_Pos (31)
6289#define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos)
6291#define GPIO_DOUT_DOUT0_Pos (0)
6292#define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos)
6294#define GPIO_DOUT_DOUT1_Pos (1)
6295#define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos)
6297#define GPIO_DOUT_DOUT2_Pos (2)
6298#define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos)
6300#define GPIO_DOUT_DOUT3_Pos (3)
6301#define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos)
6303#define GPIO_DOUT_DOUT4_Pos (4)
6304#define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos)
6306#define GPIO_DOUT_DOUT5_Pos (5)
6307#define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos)
6309#define GPIO_DOUT_DOUT6_Pos (6)
6310#define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos)
6312#define GPIO_DOUT_DOUT7_Pos (7)
6313#define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos)
6315#define GPIO_DOUT_DOUT8_Pos (8)
6316#define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos)
6318#define GPIO_DOUT_DOUT9_Pos (9)
6319#define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos)
6321#define GPIO_DOUT_DOUT10_Pos (10)
6322#define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos)
6324#define GPIO_DOUT_DOUT11_Pos (11)
6325#define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos)
6327#define GPIO_DOUT_DOUT12_Pos (12)
6328#define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos)
6330#define GPIO_DOUT_DOUT13_Pos (13)
6331#define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos)
6333#define GPIO_DOUT_DOUT14_Pos (14)
6334#define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos)
6336#define GPIO_DOUT_DOUT15_Pos (15)
6337#define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos)
6339#define GPIO_DATMSK_DMASK0_Pos (0)
6340#define GPIO_DATMSK_DMASK0_Msk (0x1ul << GPIO_DATMSK_DMASK0_Pos)
6342#define GPIO_DATMSK_DMASK1_Pos (1)
6343#define GPIO_DATMSK_DMASK1_Msk (0x1ul << GPIO_DATMSK_DMASK1_Pos)
6345#define GPIO_DATMSK_DMASK2_Pos (2)
6346#define GPIO_DATMSK_DMASK2_Msk (0x1ul << GPIO_DATMSK_DMASK2_Pos)
6348#define GPIO_DATMSK_DMASK3_Pos (3)
6349#define GPIO_DATMSK_DMASK3_Msk (0x1ul << GPIO_DATMSK_DMASK3_Pos)
6351#define GPIO_DATMSK_DMASK4_Pos (4)
6352#define GPIO_DATMSK_DMASK4_Msk (0x1ul << GPIO_DATMSK_DMASK4_Pos)
6354#define GPIO_DATMSK_DMASK5_Pos (5)
6355#define GPIO_DATMSK_DMASK5_Msk (0x1ul << GPIO_DATMSK_DMASK5_Pos)
6357#define GPIO_DATMSK_DMASK6_Pos (6)
6358#define GPIO_DATMSK_DMASK6_Msk (0x1ul << GPIO_DATMSK_DMASK6_Pos)
6360#define GPIO_DATMSK_DMASK7_Pos (7)
6361#define GPIO_DATMSK_DMASK7_Msk (0x1ul << GPIO_DATMSK_DMASK7_Pos)
6363#define GPIO_DATMSK_DMASK8_Pos (8)
6364#define GPIO_DATMSK_DMASK8_Msk (0x1ul << GPIO_DATMSK_DMASK8_Pos)
6366#define GPIO_DATMSK_DMASK9_Pos (9)
6367#define GPIO_DATMSK_DMASK9_Msk (0x1ul << GPIO_DATMSK_DMASK9_Pos)
6369#define GPIO_DATMSK_DMASK10_Pos (10)
6370#define GPIO_DATMSK_DMASK10_Msk (0x1ul << GPIO_DATMSK_DMASK10_Pos)
6372#define GPIO_DATMSK_DMASK11_Pos (11)
6373#define GPIO_DATMSK_DMASK11_Msk (0x1ul << GPIO_DATMSK_DMASK11_Pos)
6375#define GPIO_DATMSK_DMASK12_Pos (12)
6376#define GPIO_DATMSK_DMASK12_Msk (0x1ul << GPIO_DATMSK_DMASK12_Pos)
6378#define GPIO_DATMSK_DMASK13_Pos (13)
6379#define GPIO_DATMSK_DMASK13_Msk (0x1ul << GPIO_DATMSK_DMASK13_Pos)
6381#define GPIO_DATMSK_DMASK14_Pos (14)
6382#define GPIO_DATMSK_DMASK14_Msk (0x1ul << GPIO_DATMSK_DMASK14_Pos)
6384#define GPIO_DATMSK_DMASK15_Pos (15)
6385#define GPIO_DATMSK_DMASK15_Msk (0x1ul << GPIO_DATMSK_DMASK15_Pos)
6387#define GPIO_PIN_PIN0_Pos (0)
6388#define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos)
6390#define GPIO_PIN_PIN1_Pos (1)
6391#define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos)
6393#define GPIO_PIN_PIN2_Pos (2)
6394#define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos)
6396#define GPIO_PIN_PIN3_Pos (3)
6397#define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos)
6399#define GPIO_PIN_PIN4_Pos (4)
6400#define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos)
6402#define GPIO_PIN_PIN5_Pos (5)
6403#define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos)
6405#define GPIO_PIN_PIN6_Pos (6)
6406#define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos)
6408#define GPIO_PIN_PIN7_Pos (7)
6409#define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos)
6411#define GPIO_PIN_PIN8_Pos (8)
6412#define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos)
6414#define GPIO_PIN_PIN9_Pos (9)
6415#define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos)
6417#define GPIO_PIN_PIN10_Pos (10)
6418#define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos)
6420#define GPIO_PIN_PIN11_Pos (11)
6421#define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos)
6423#define GPIO_PIN_PIN12_Pos (12)
6424#define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos)
6426#define GPIO_PIN_PIN13_Pos (13)
6427#define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos)
6429#define GPIO_PIN_PIN14_Pos (14)
6430#define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos)
6432#define GPIO_PIN_PIN15_Pos (15)
6433#define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos)
6435#define GPIO_DBEN_DBEN0_Pos (0)
6436#define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos)
6438#define GPIO_DBEN_DBEN1_Pos (1)
6439#define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos)
6441#define GPIO_DBEN_DBEN2_Pos (2)
6442#define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos)
6444#define GPIO_DBEN_DBEN3_Pos (3)
6445#define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos)
6447#define GPIO_DBEN_DBEN4_Pos (4)
6448#define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos)
6450#define GPIO_DBEN_DBEN5_Pos (5)
6451#define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos)
6453#define GPIO_DBEN_DBEN6_Pos (6)
6454#define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos)
6456#define GPIO_DBEN_DBEN7_Pos (7)
6457#define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos)
6459#define GPIO_DBEN_DBEN8_Pos (8)
6460#define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos)
6462#define GPIO_DBEN_DBEN9_Pos (9)
6463#define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos)
6465#define GPIO_DBEN_DBEN10_Pos (10)
6466#define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos)
6468#define GPIO_DBEN_DBEN11_Pos (11)
6469#define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos)
6471#define GPIO_DBEN_DBEN12_Pos (12)
6472#define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos)
6474#define GPIO_DBEN_DBEN13_Pos (13)
6475#define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos)
6477#define GPIO_DBEN_DBEN14_Pos (14)
6478#define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos)
6480#define GPIO_DBEN_DBEN15_Pos (15)
6481#define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos)
6483#define GPIO_INTTYPE_TYPE0_Pos (0)
6484#define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos)
6486#define GPIO_INTTYPE_TYPE1_Pos (1)
6487#define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos)
6489#define GPIO_INTTYPE_TYPE2_Pos (2)
6490#define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos)
6492#define GPIO_INTTYPE_TYPE3_Pos (3)
6493#define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos)
6495#define GPIO_INTTYPE_TYPE4_Pos (4)
6496#define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos)
6498#define GPIO_INTTYPE_TYPE5_Pos (5)
6499#define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos)
6501#define GPIO_INTTYPE_TYPE6_Pos (6)
6502#define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos)
6504#define GPIO_INTTYPE_TYPE7_Pos (7)
6505#define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos)
6507#define GPIO_INTTYPE_TYPE8_Pos (8)
6508#define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos)
6510#define GPIO_INTTYPE_TYPE9_Pos (9)
6511#define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos)
6513#define GPIO_INTTYPE_TYPE10_Pos (10)
6514#define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos)
6516#define GPIO_INTTYPE_TYPE11_Pos (11)
6517#define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos)
6519#define GPIO_INTTYPE_TYPE12_Pos (12)
6520#define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos)
6522#define GPIO_INTTYPE_TYPE13_Pos (13)
6523#define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos)
6525#define GPIO_INTTYPE_TYPE14_Pos (14)
6526#define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos)
6528#define GPIO_INTTYPE_TYPE15_Pos (15)
6529#define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos)
6531#define GPIO_INTEN_FLIEN0_Pos (0)
6532#define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos)
6534#define GPIO_INTEN_FLIEN1_Pos (1)
6535#define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos)
6537#define GPIO_INTEN_FLIEN2_Pos (2)
6538#define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos)
6540#define GPIO_INTEN_FLIEN3_Pos (3)
6541#define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos)
6543#define GPIO_INTEN_FLIEN4_Pos (4)
6544#define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos)
6546#define GPIO_INTEN_FLIEN5_Pos (5)
6547#define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos)
6549#define GPIO_INTEN_FLIEN6_Pos (6)
6550#define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos)
6552#define GPIO_INTEN_FLIEN7_Pos (7)
6553#define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos)
6555#define GPIO_INTEN_FLIEN8_Pos (8)
6556#define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos)
6558#define GPIO_INTEN_FLIEN9_Pos (9)
6559#define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos)
6561#define GPIO_INTEN_FLIEN10_Pos (10)
6562#define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos)
6564#define GPIO_INTEN_FLIEN11_Pos (11)
6565#define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos)
6567#define GPIO_INTEN_FLIEN12_Pos (12)
6568#define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos)
6570#define GPIO_INTEN_FLIEN13_Pos (13)
6571#define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos)
6573#define GPIO_INTEN_FLIEN14_Pos (14)
6574#define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos)
6576#define GPIO_INTEN_FLIEN15_Pos (15)
6577#define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos)
6579#define GPIO_INTEN_RHIEN0_Pos (16)
6580#define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos)
6582#define GPIO_INTEN_RHIEN1_Pos (17)
6583#define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos)
6585#define GPIO_INTEN_RHIEN2_Pos (18)
6586#define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos)
6588#define GPIO_INTEN_RHIEN3_Pos (19)
6589#define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos)
6591#define GPIO_INTEN_RHIEN4_Pos (20)
6592#define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos)
6594#define GPIO_INTEN_RHIEN5_Pos (21)
6595#define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos)
6597#define GPIO_INTEN_RHIEN6_Pos (22)
6598#define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos)
6600#define GPIO_INTEN_RHIEN7_Pos (23)
6601#define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos)
6603#define GPIO_INTEN_RHIEN8_Pos (24)
6604#define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos)
6606#define GPIO_INTEN_RHIEN9_Pos (25)
6607#define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos)
6609#define GPIO_INTEN_RHIEN10_Pos (26)
6610#define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos)
6612#define GPIO_INTEN_RHIEN11_Pos (27)
6613#define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos)
6615#define GPIO_INTEN_RHIEN12_Pos (28)
6616#define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos)
6618#define GPIO_INTEN_RHIEN13_Pos (29)
6619#define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos)
6621#define GPIO_INTEN_RHIEN14_Pos (30)
6622#define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos)
6624#define GPIO_INTEN_RHIEN15_Pos (31)
6625#define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos)
6627#define GPIO_INTSRC_INTSRC0_Pos (0)
6628#define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos)
6630#define GPIO_INTSRC_INTSRC1_Pos (1)
6631#define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos)
6633#define GPIO_INTSRC_INTSRC2_Pos (2)
6634#define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos)
6636#define GPIO_INTSRC_INTSRC3_Pos (3)
6637#define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos)
6639#define GPIO_INTSRC_INTSRC4_Pos (4)
6640#define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos)
6642#define GPIO_INTSRC_INTSRC5_Pos (5)
6643#define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos)
6645#define GPIO_INTSRC_INTSRC6_Pos (6)
6646#define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos)
6648#define GPIO_INTSRC_INTSRC7_Pos (7)
6649#define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos)
6651#define GPIO_INTSRC_INTSRC8_Pos (8)
6652#define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos)
6654#define GPIO_INTSRC_INTSRC9_Pos (9)
6655#define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos)
6657#define GPIO_INTSRC_INTSRC10_Pos (10)
6658#define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos)
6660#define GPIO_INTSRC_INTSRC11_Pos (11)
6661#define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos)
6663#define GPIO_INTSRC_INTSRC12_Pos (12)
6664#define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos)
6666#define GPIO_INTSRC_INTSRC13_Pos (13)
6667#define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos)
6669#define GPIO_INTSRC_INTSRC14_Pos (14)
6670#define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos)
6672#define GPIO_INTSRC_INTSRC15_Pos (15)
6673#define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos)
6675#define GPIO_PUEN_PUEN0_Pos (0)
6676#define GPIO_PUEN_PUEN0_Msk (0x1ul << GPIO_PUEN_PUEN0_Pos)
6678#define GPIO_PUEN_PUEN1_Pos (1)
6679#define GPIO_PUEN_PUEN1_Msk (0x1ul << GPIO_PUEN_PUEN1_Pos)
6681#define GPIO_PUEN_PUEN2_Pos (2)
6682#define GPIO_PUEN_PUEN2_Msk (0x1ul << GPIO_PUEN_PUEN2_Pos)
6684#define GPIO_PUEN_PUEN3_Pos (3)
6685#define GPIO_PUEN_PUEN3_Msk (0x1ul << GPIO_PUEN_PUEN3_Pos)
6687#define GPIO_PUEN_PUEN4_Pos (4)
6688#define GPIO_PUEN_PUEN4_Msk (0x1ul << GPIO_PUEN_PUEN4_Pos)
6690#define GPIO_PUEN_PUEN5_Pos (5)
6691#define GPIO_PUEN_PUEN5_Msk (0x1ul << GPIO_PUEN_PUEN5_Pos)
6693#define GPIO_PUEN_PUEN6_Pos (6)
6694#define GPIO_PUEN_PUEN6_Msk (0x1ul << GPIO_PUEN_PUEN6_Pos)
6696#define GPIO_PUEN_PUEN7_Pos (7)
6697#define GPIO_PUEN_PUEN7_Msk (0x1ul << GPIO_PUEN_PUEN7_Pos)
6699#define GPIO_PUEN_PUEN8_Pos (8)
6700#define GPIO_PUEN_PUEN8_Msk (0x1ul << GPIO_PUEN_PUEN8_Pos)
6702#define GPIO_PUEN_PUEN9_Pos (9)
6703#define GPIO_PUEN_PUEN9_Msk (0x1ul << GPIO_PUEN_PUEN9_Pos)
6705#define GPIO_PUEN_PUEN10_Pos (10)
6706#define GPIO_PUEN_PUEN10_Msk (0x1ul << GPIO_PUEN_PUEN10_Pos)
6708#define GPIO_PUEN_PUEN11_Pos (11)
6709#define GPIO_PUEN_PUEN11_Msk (0x1ul << GPIO_PUEN_PUEN11_Pos)
6711#define GPIO_PUEN_PUEN12_Pos (12)
6712#define GPIO_PUEN_PUEN12_Msk (0x1ul << GPIO_PUEN_PUEN12_Pos)
6714#define GPIO_PUEN_PUEN13_Pos (13)
6715#define GPIO_PUEN_PUEN13_Msk (0x1ul << GPIO_PUEN_PUEN13_Pos)
6717#define GPIO_PUEN_PUEN14_Pos (14)
6718#define GPIO_PUEN_PUEN14_Msk (0x1ul << GPIO_PUEN_PUEN14_Pos)
6720#define GPIO_PUEN_PUEN15_Pos (15)
6721#define GPIO_PUEN_PUEN15_Msk (0x1ul << GPIO_PUEN_PUEN15_Pos)
6723#define GPIO_INTSTS_FLISTS0_Pos (0)
6724#define GPIO_INTSTS_FLISTS0_Msk (0x1ul << GPIO_INTSTS_FLISTS0_Pos)
6726#define GPIO_INTSTS_FLISTS1_Pos (1)
6727#define GPIO_INTSTS_FLISTS1_Msk (0x1ul << GPIO_INTSTS_FLISTS1_Pos)
6729#define GPIO_INTSTS_FLISTS2_Pos (2)
6730#define GPIO_INTSTS_FLISTS2_Msk (0x1ul << GPIO_INTSTS_FLISTS2_Pos)
6732#define GPIO_INTSTS_FLISTS3_Pos (3)
6733#define GPIO_INTSTS_FLISTS3_Msk (0x1ul << GPIO_INTSTS_FLISTS3_Pos)
6735#define GPIO_INTSTS_FLISTS4_Pos (4)
6736#define GPIO_INTSTS_FLISTS4_Msk (0x1ul << GPIO_INTSTS_FLISTS4_Pos)
6738#define GPIO_INTSTS_FLISTS5_Pos (5)
6739#define GPIO_INTSTS_FLISTS5_Msk (0x1ul << GPIO_INTSTS_FLISTS5_Pos)
6741#define GPIO_INTSTS_FLISTS6_Pos (6)
6742#define GPIO_INTSTS_FLISTS6_Msk (0x1ul << GPIO_INTSTS_FLISTS6_Pos)
6744#define GPIO_INTSTS_FLISTS7_Pos (7)
6745#define GPIO_INTSTS_FLISTS7_Msk (0x1ul << GPIO_INTSTS_FLISTS7_Pos)
6747#define GPIO_INTSTS_FLISTS8_Pos (8)
6748#define GPIO_INTSTS_FLISTS8_Msk (0x1ul << GPIO_INTSTS_FLISTS8_Pos)
6750#define GPIO_INTSTS_FLISTS9_Pos (9)
6751#define GPIO_INTSTS_FLISTS9_Msk (0x1ul << GPIO_INTSTS_FLISTS9_Pos)
6753#define GPIO_INTSTS_FLISTS10_Pos (10)
6754#define GPIO_INTSTS_FLISTS10_Msk (0x1ul << GPIO_INTSTS_FLISTS10_Pos)
6756#define GPIO_INTSTS_FLISTS11_Pos (11)
6757#define GPIO_INTSTS_FLISTS11_Msk (0x1ul << GPIO_INTSTS_FLISTS11_Pos)
6759#define GPIO_INTSTS_FLISTS12_Pos (12)
6760#define GPIO_INTSTS_FLISTS12_Msk (0x1ul << GPIO_INTSTS_FLISTS12_Pos)
6762#define GPIO_INTSTS_FLISTS13_Pos (13)
6763#define GPIO_INTSTS_FLISTS13_Msk (0x1ul << GPIO_INTSTS_FLISTS13_Pos)
6765#define GPIO_INTSTS_FLISTS14_Pos (14)
6766#define GPIO_INTSTS_FLISTS14_Msk (0x1ul << GPIO_INTSTS_FLISTS14_Pos)
6768#define GPIO_INTSTS_FLISTS15_Pos (15)
6769#define GPIO_INTSTS_FLISTS15_Msk (0x1ul << GPIO_INTSTS_FLISTS15_Pos)
6771#define GPIO_INTSTS_RHISTS0_Pos (16)
6772#define GPIO_INTSTS_RHISTS0_Msk (0x1ul << GPIO_INTSTS_RHISTS0_Pos)
6774#define GPIO_INTSTS_RHISTS1_Pos (17)
6775#define GPIO_INTSTS_RHISTS1_Msk (0x1ul << GPIO_INTSTS_RHISTS1_Pos)
6777#define GPIO_INTSTS_RHISTS2_Pos (18)
6778#define GPIO_INTSTS_RHISTS2_Msk (0x1ul << GPIO_INTSTS_RHISTS2_Pos)
6780#define GPIO_INTSTS_RHISTS3_Pos (19)
6781#define GPIO_INTSTS_RHISTS3_Msk (0x1ul << GPIO_INTSTS_RHISTS3_Pos)
6783#define GPIO_INTSTS_RHISTS4_Pos (20)
6784#define GPIO_INTSTS_RHISTS4_Msk (0x1ul << GPIO_INTSTS_RHISTS4_Pos)
6786#define GPIO_INTSTS_RHISTS5_Pos (21)
6787#define GPIO_INTSTS_RHISTS5_Msk (0x1ul << GPIO_INTSTS_RHISTS5_Pos)
6789#define GPIO_INTSTS_RHISTS6_Pos (22)
6790#define GPIO_INTSTS_RHISTS6_Msk (0x1ul << GPIO_INTSTS_RHISTS6_Pos)
6792#define GPIO_INTSTS_RHISTS7_Pos (23)
6793#define GPIO_INTSTS_RHISTS7_Msk (0x1ul << GPIO_INTSTS_RHISTS7_Pos)
6795#define GPIO_INTSTS_RHISTS8_Pos (24)
6796#define GPIO_INTSTS_RHISTS8_Msk (0x1ul << GPIO_INTSTS_RHISTS8_Pos)
6798#define GPIO_INTSTS_RHISTS9_Pos (25)
6799#define GPIO_INTSTS_RHISTS9_Msk (0x1ul << GPIO_INTSTS_RHISTS9_Pos)
6801#define GPIO_INTSTS_RHISTS10_Pos (26)
6802#define GPIO_INTSTS_RHISTS10_Msk (0x1ul << GPIO_INTSTS_RHISTS10_Pos)
6804#define GPIO_INTSTS_RHISTS11_Pos (27)
6805#define GPIO_INTSTS_RHISTS11_Msk (0x1ul << GPIO_INTSTS_RHISTS11_Pos)
6807#define GPIO_INTSTS_RHISTS12_Pos (28)
6808#define GPIO_INTSTS_RHISTS12_Msk (0x1ul << GPIO_INTSTS_RHISTS12_Pos)
6810#define GPIO_INTSTS_RHISTS13_Pos (29)
6811#define GPIO_INTSTS_RHISTS13_Msk (0x1ul << GPIO_INTSTS_RHISTS13_Pos)
6813#define GPIO_INTSTS_RHISTS14_Pos (30)
6814#define GPIO_INTSTS_RHISTS14_Msk (0x1ul << GPIO_INTSTS_RHISTS14_Pos)
6816#define GPIO_INTSTS_RHISTS15_Pos (31)
6817#define GPIO_INTSTS_RHISTS15_Msk (0x1ul << GPIO_INTSTS_RHISTS15_Pos)
6819#define GPIO_DBCTL_DBCLKSEL_Pos (0)
6820#define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos)
6822#define GPIO_DBCTL_DBCLKSRC_Pos (4)
6823#define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos)
6825#define GPIO_DBCTL_ICLKON_Pos (5)
6826#define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /* GPIO_CONST */ /* end of GPIO register group */
6831
6832/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
6838typedef struct
6839{
6840
6841
7000 __IO uint32_t CTLn;
7001 __IO uint32_t SAn;
7002 __IO uint32_t DAn;
7003 __IO uint32_t CNTn;
7005 __I uint32_t RESERVE0[1];
7007 __I uint32_t CSAn;
7008 __I uint32_t CDAn;
7009 __I uint32_t CCNTn;
7010 __IO uint32_t INTENn;
7011 __IO uint32_t INTSTSn;
7012 __IO uint32_t TOCn;
7014} PDMA_CH_T;
7015
7016
7017
7018typedef struct
7019{
7020
7021
7167 __IO uint32_t CTL;
7168 __IO uint32_t DMASA;
7170 __I uint32_t RESERVE0[1];
7172 __IO uint32_t DMABCNT;
7174 __I uint32_t RESERVE1[1];
7176 __I uint32_t DMACSA;
7178 __I uint32_t RESERVE2[1];
7180 __I uint32_t DMACBCNT;
7181 __IO uint32_t DMAINTEN;
7182 __IO uint32_t DMAISTS;
7184 __I uint32_t RESERVE3[22];
7186 __IO uint32_t DAT;
7187 __IO uint32_t SEED;
7188 __I uint32_t CHECKSUM;
7190} DMA_CRC_T;
7191
7192
7193
7194typedef struct
7195{
7196
7197
7290 __IO uint32_t GCTL;
7291 __IO uint32_t REQSEL0;
7292 __IO uint32_t REQSEL1;
7293 __I uint32_t GINTSTS;
7295} DMA_GCR_T;
7296
7302#define PDMA_CH_CTLn_CHEN_Pos (0)
7303#define PDMA_CH_CTLn_CHEN_Msk (0x1ul << PDMA_CH_CTLn_CHEN_Pos)
7305#define PDMA_CH_CTLn_SWRST_Pos (1)
7306#define PDMA_CH_CTLn_SWRST_Msk (0x1ul << PDMA_CH_CTLn_SWRST_Pos)
7308#define PDMA_CH_CTLn_SASEL_Pos (4)
7309#define PDMA_CH_CTLn_SASEL_Msk (0x3ul << PDMA_CH_CTLn_SASEL_Pos)
7311#define PDMA_CH_CTLn_DASEL_Pos (6)
7312#define PDMA_CH_CTLn_DASEL_Msk (0x3ul << PDMA_CH_CTLn_DASEL_Pos)
7314#define PDMA_CH_CTLn_TOUTEN_Pos (12)
7315#define PDMA_CH_CTLn_TOUTEN_Msk (0x1ul << PDMA_CH_CTLn_TOUTEN_Pos)
7317#define PDMA_CH_CTLn_TXWIDTH_Pos (19)
7318#define PDMA_CH_CTLn_TXWIDTH_Msk (0x3ul << PDMA_CH_CTLn_TXWIDTH_Pos)
7320#define PDMA_CH_CTLn_TRIGEN_Pos (23)
7321#define PDMA_CH_CTLn_TRIGEN_Msk (0x1ul << PDMA_CH_CTLn_TRIGEN_Pos)
7323#define PDMA_CH_SAn_SA_Pos (0)
7324#define PDMA_CH_SAn_SA_Msk (0xfffffffful << PDMA_CH_SAn_SA_Pos)
7326#define PDMA_CH_DAn_DA_Pos (0)
7327#define PDMA_CH_DAn_DA_Msk (0xfffffffful << PDMA_CH_DAn_DA_Pos)
7329#define PDMA_CH_CNTn_TCNT_Pos (0)
7330#define PDMA_CH_CNTn_TCNT_Msk (0xfffful << PDMA_CH_CNTn_TCNT_Pos)
7332#define PDMA_CH_CNTn_PCNTITH_Pos (16)
7333#define PDMA_CH_CNTn_PCNTITH_Msk (0xfffful << PDMA_CH_CNTn_PCNTITH_Pos)
7335#define PDMA_CH_CSAn_CSA_Pos (0)
7336#define PDMA_CH_CSAn_CSA_Msk (0xfffffffful << PDMA_CH_CSAn_CSA_Pos)
7338#define PDMA_CH_CDAn_CDA_Pos (0)
7339#define PDMA_CH_CDAn_CDA_Msk (0xfffffffful << PDMA_CH_CDAn_CDA_Pos)
7341#define PDMA_CH_CCNTn_CCNT_Pos (0)
7342#define PDMA_CH_CCNTn_CCNT_Msk (0xfffful << PDMA_CH_CCNTn_CCNT_Pos)
7344#define PDMA_CH_INTENn_TABTIEN_Pos (0)
7345#define PDMA_CH_INTENn_TABTIEN_Msk (0x1ul << PDMA_CH_INTENn_TABTIEN_Pos)
7347#define PDMA_CH_INTENn_TDIEN_Pos (1)
7348#define PDMA_CH_INTENn_TDIEN_Msk (0x1ul << PDMA_CH_INTENn_TDIEN_Pos)
7350#define PDMA_CH_INTENn_TOUTIEN_Pos (6)
7351#define PDMA_CH_INTENn_TOUTIEN_Msk (0x1ul << PDMA_CH_INTENn_TOUTIEN_Pos)
7353#define PDMA_CH_INTENn_PCNTIEN_Pos (8)
7354#define PDMA_CH_INTENn_PCNTIEN_Msk (0x1ul << PDMA_CH_INTENn_PCNTIEN_Pos)
7356#define PDMA_CH_INTSTSn_TABTIF_Pos (0)
7357#define PDMA_CH_INTSTSn_TABTIF_Msk (0x1ul << PDMA_CH_INTSTSn_TABTIF_Pos)
7359#define PDMA_CH_INTSTSn_TDIF_Pos (1)
7360#define PDMA_CH_INTSTSn_TDIF_Msk (0x1ul << PDMA_CH_INTSTSn_TDIF_Pos)
7362#define PDMA_CH_INTSTSn_TOUTIF_Pos (6)
7363#define PDMA_CH_INTSTSn_TOUTIF_Msk (0x1ul << PDMA_CH_INTSTSn_TOUTIF_Pos)
7365#define PDMA_CH_INTSTSn_PCNTIF_Pos (8)
7366#define PDMA_CH_INTSTSn_PCNTIF_Msk (0x1ul << PDMA_CH_INTSTSn_PCNTIF_Pos)
7368#define PDMA_CH_TOCn_TOC_Pos (0)
7369#define PDMA_CH_TOCn_TOC_Msk (0xfffful << PDMA_CH_TOCn_TOC_Pos)
7371#define PDMA_CH_TOCn_TPSC_Pos (16)
7372#define PDMA_CH_TOCn_TPSC_Msk (0x7ul << PDMA_CH_TOCn_TPSC_Pos) /* PDMA_CH_CONST */
7375
7376
7382#define DMA_CRC_CTL_CRCEN_Pos (0)
7383#define DMA_CRC_CTL_CRCEN_Msk (0x1ul << DMA_CRC_CTL_CRCEN_Pos)
7385#define DMA_CRC_CTL_CRCRST_Pos (1)
7386#define DMA_CRC_CTL_CRCRST_Msk (0x1ul << DMA_CRC_CTL_CRCRST_Pos)
7388#define DMA_CRC_CTL_TRIGEN_Pos (23)
7389#define DMA_CRC_CTL_TRIGEN_Msk (0x1ul << DMA_CRC_CTL_TRIGEN_Pos)
7391#define DMA_CRC_CTL_DATREV_Pos (24)
7392#define DMA_CRC_CTL_DATREV_Msk (0x1ul << DMA_CRC_CTL_DATREV_Pos)
7394#define DMA_CRC_CTL_CHKSREV_Pos (25)
7395#define DMA_CRC_CTL_CHKSREV_Msk (0x1ul << DMA_CRC_CTL_CHKSREV_Pos)
7397#define DMA_CRC_CTL_DATFMT_Pos (26)
7398#define DMA_CRC_CTL_DATFMT_Msk (0x1ul << DMA_CRC_CTL_DATFMT_Pos)
7400#define DMA_CRC_CTL_CHKSFMT_Pos (27)
7401#define DMA_CRC_CTL_CHKSFMT_Msk (0x1ul << DMA_CRC_CTL_CHKSFMT_Pos)
7403#define DMA_CRC_CTL_DATLEN_Pos (28)
7404#define DMA_CRC_CTL_DATLEN_Msk (0x3ul << DMA_CRC_CTL_DATLEN_Pos)
7406#define DMA_CRC_CTL_CRCMODE_Pos (30)
7407#define DMA_CRC_CTL_CRCMODE_Msk (0x3ul << DMA_CRC_CTL_CRCMODE_Pos)
7409#define DMA_CRC_DMASA_SA_Pos (0)
7410#define DMA_CRC_DMASA_SA_Msk (0xfffffffful << DMA_CRC_DMASA_SA_Pos)
7412#define DMA_CRC_DMABCNT_BCNT_Pos (0)
7413#define DMA_CRC_DMABCNT_BCNT_Msk (0xfffful << DMA_CRC_DMABCNT_BCNT_Pos)
7415#define DMA_CRC_DMACSA_CSA_Pos (0)
7416#define DMA_CRC_DMACSA_CSA_Msk (0xfffffffful << DMA_CRC_DMACSA_CSA_Pos)
7418#define DMA_CRC_DMACBCNT_CBCNT_Pos (0)
7419#define DMA_CRC_DMACBCNT_CBCNT_Msk (0xfffful << DMA_CRC_DMACBCNT_CBCNT_Pos)
7421#define DMA_CRC_DMAINTEN_TABTIEN_Pos (0)
7422#define DMA_CRC_DMAINTEN_TABTIEN_Msk (0x1ul << DMA_CRC_DMAINTEN_TABTIEN_Pos)
7424#define DMA_CRC_DMAINTEN_TDIEN_Pos (1)
7425#define DMA_CRC_DMAINTEN_TDIEN_Msk (0x1ul << DMA_CRC_DMAINTEN_TDIEN_Pos)
7427#define DMA_CRC_DMAISTS_TABTIF_Pos (0)
7428#define DMA_CRC_DMAISTS_TABTIF_Msk (0x1ul << DMA_CRC_DMAISTS_TABTIF_Pos)
7430#define DMA_CRC_DMAISTS_TDIF_Pos (1)
7431#define DMA_CRC_DMAISTS_TDIF_Msk (0x1ul << DMA_CRC_DMAISTS_TDIF_Pos)
7433#define DMA_CRC_DAT_DATA_Pos (0)
7434#define DMA_CRC_DAT_DATA_Msk (0xfffffffful << DMA_CRC_DAT_DATA_Pos)
7436#define DMA_CRC_SEED_SEED_Pos (0)
7437#define DMA_CRC_SEED_SEED_Msk (0xfffffffful << DMA_CRC_SEED_SEED_Pos)
7439#define DMA_CRC_CHECKSUM_CHECKSUM_Pos (0)
7440#define DMA_CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << DMA_CRC_CHECKSUM_CHECKSUM_Pos) /* CRC_CONST */
7443
7449#define DMA_GCR_GCTL_CKEN1_Pos (9)
7450#define DMA_GCR_GCTL_CKEN1_Msk (0x1ul << DMA_GCR_GCTL_CKEN1_Pos)
7452#define DMA_GCR_GCTL_CKEN2_Pos (10)
7453#define DMA_GCR_GCTL_CKEN2_Msk (0x1ul << DMA_GCR_GCTL_CKEN2_Pos)
7455#define DMA_GCR_GCTL_CKEN3_Pos (11)
7456#define DMA_GCR_GCTL_CKEN3_Msk (0x1ul << DMA_GCR_GCTL_CKEN3_Pos)
7458#define DMA_GCR_GCTL_CKEN4_Pos (12)
7459#define DMA_GCR_GCTL_CKEN4_Msk (0x1ul << DMA_GCR_GCTL_CKEN4_Pos)
7461#define DMA_GCR_GCTL_CKENCRC_Pos (24)
7462#define DMA_GCR_GCTL_CKENCRC_Msk (0x1ul << DMA_GCR_GCTL_CKENCRC_Pos)
7464#define DMA_GCR_REQSEL0_REQSRC1_Pos (8)
7465#define DMA_GCR_REQSEL0_REQSRC1_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC1_Pos)
7467#define DMA_GCR_REQSEL0_REQSRC2_Pos (16)
7468#define DMA_GCR_REQSEL0_REQSRC2_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC2_Pos)
7470#define DMA_GCR_REQSEL0_REQSRC3_Pos (24)
7471#define DMA_GCR_REQSEL0_REQSRC3_Msk (0x1ful << DMA_GCR_REQSEL0_REQSRC3_Pos)
7473#define DMA_GCR_REQSEL1_REQSRC4_Pos (0)
7474#define DMA_GCR_REQSEL1_REQSRC4_Msk (0x1ful << DMA_GCR_REQSEL1_REQSRC4_Pos)
7476#define DMA_GCR_GINTSTS_IF1_Pos (1)
7477#define DMA_GCR_GINTSTS_IF1_Msk (0x1ul << DMA_GCR_GINTSTS_IF1_Pos)
7479#define DMA_GCR_GINTSTS_IF2_Pos (2)
7480#define DMA_GCR_GINTSTS_IF2_Msk (0x1ul << DMA_GCR_GINTSTS_IF2_Pos)
7482#define DMA_GCR_GINTSTS_IF3_Pos (3)
7483#define DMA_GCR_GINTSTS_IF3_Msk (0x1ul << DMA_GCR_GINTSTS_IF3_Pos)
7485#define DMA_GCR_GINTSTS_IF4_Pos (4)
7486#define DMA_GCR_GINTSTS_IF4_Msk (0x1ul << DMA_GCR_GINTSTS_IF4_Pos)
7488#define DMA_GCR_GINTSTS_IFCRC_Pos (16)
7489#define DMA_GCR_GINTSTS_IFCRC_Msk (0x1ul << DMA_GCR_GINTSTS_IFCRC_Pos) /* PDMA_GCR_CONST */ /* end of DMA register group */
7493
7494
7495/*---------------------- Timer Controller -------------------------*/
7501typedef struct
7502{
7503
7504
7746 __IO uint32_t CTL;
7747 __IO uint32_t PRECNT;
7748 __IO uint32_t CMP;
7749 __IO uint32_t INTEN;
7750 __IO uint32_t INTSTS;
7751 __IO uint32_t CNT;
7752 __I uint32_t CAP;
7754 __I uint32_t RESERVE0[1];
7756 __IO uint32_t ECTL;
7758} TIMER_T;
7759
7764#define TIMER_CTL_CNTEN_Pos (0)
7765#define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos)
7767#define TIMER_CTL_RSTCNT_Pos (1)
7768#define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos)
7770#define TIMER_CTL_WKEN_Pos (2)
7771#define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos)
7773#define TIMER_CTL_ICEDEBUG_Pos (3)
7774#define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos)
7776#define TIMER_CTL_OPMODE_Pos (4)
7777#define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos)
7779#define TIMER_CTL_ACTSTS_Pos (7)
7780#define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos)
7782#define TIMER_CTL_TRGADC_Pos (8)
7783#define TIMER_CTL_TRGADC_Msk (0x1ul << TIMER_CTL_TRGADC_Pos)
7785#define TIMER_CTL_TRGPDMA_Pos (10)
7786#define TIMER_CTL_TRGPDMA_Msk (0x1ul << TIMER_CTL_TRGPDMA_Pos)
7788#define TIMER_CTL_TRGSSEL_Pos (11)
7789#define TIMER_CTL_TRGSSEL_Msk (0x1ul << TIMER_CTL_TRGSSEL_Pos)
7791#define TIMER_CTL_EXTCNTEN_Pos (12)
7792#define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos)
7794#define TIMER_CTL_CNTPHASE_Pos (13)
7795#define TIMER_CTL_CNTPHASE_Msk (0x1ul << TIMER_CTL_CNTPHASE_Pos)
7797#define TIMER_CTL_CNTDBEN_Pos (14)
7798#define TIMER_CTL_CNTDBEN_Msk (0x1ul << TIMER_CTL_CNTDBEN_Pos)
7800#define TIMER_CTL_CAPEN_Pos (16)
7801#define TIMER_CTL_CAPEN_Msk (0x1ul << TIMER_CTL_CAPEN_Pos)
7803#define TIMER_CTL_CAPFUNCS_Pos (17)
7804#define TIMER_CTL_CAPFUNCS_Msk (0x1ul << TIMER_CTL_CAPFUNCS_Pos)
7806#define TIMER_CTL_CAPEDGE_Pos (18)
7807#define TIMER_CTL_CAPEDGE_Msk (0x3ul << TIMER_CTL_CAPEDGE_Pos)
7809#define TIMER_CTL_CAPCNTMD_Pos (20)
7810#define TIMER_CTL_CAPCNTMD_Msk (0x1ul << TIMER_CTL_CAPCNTMD_Pos)
7812#define TIMER_CTL_CAPDBEN_Pos (22)
7813#define TIMER_CTL_CAPDBEN_Msk (0x1ul << TIMER_CTL_CAPDBEN_Pos)
7815#define TIMER_CTL_CMPCTL_Pos (23)
7816#define TIMER_CTL_CMPCTL_Msk (0x1ul << TIMER_CTL_CMPCTL_Pos)
7818#define TIMER_CTL_INTRTGEN_Pos (24)
7819#define TIMER_CTL_INTRTGEN_Msk (0x1ul << TIMER_CTL_INTRTGEN_Pos)
7821#define TIMER_CTL_INTRTGMD_Pos (25)
7822#define TIMER_CTL_INTRTGMD_Msk (0x1ul << TIMER_CTL_INTRTGMD_Pos)
7824#define TIMER_CTL_TRGPWM_Pos (28)
7825#define TIMER_CTL_TRGPWM_Msk (0x1ul << TIMER_CTL_TRGPWM_Pos)
7827#define TIMER_PRECNT_PSC_Pos (0)
7828#define TIMER_PRECNT_PSC_Msk (0xfful << TIMER_PRECNT_PSC_Pos)
7830#define TIMER_CMP_CMPDAT_Pos (0)
7831#define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_P)
7833#define TIMER_INTEN_CNTIEN_Pos (0)
7834#define TIMER_INTEN_CNTIEN_Msk (0x1ul << TIMER_INTEN_CNTIEN_Pos)
7836#define TIMER_INTEN_CAPIEN_Pos (1)
7837#define TIMER_INTEN_CAPIEN_Msk (0x1ul << TIMER_INTEN_CAPIEN_Pos)
7839#define TIMER_INTSTS_CNTIF_Pos (0)
7840#define TIMER_INTSTS_CNTIF_Msk (0x1ul << TIMER_INTSTS_CNTIF_Pos)
7842#define TIMER_INTSTS_CAPIF_Pos (1)
7843#define TIMER_INTSTS_CAPIF_Msk (0x1ul << TIMER_INTSTS_CAPIF_Pos)
7845#define TIMER_INTSTS_TWKF_Pos (4)
7846#define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos)
7848#define TIMER_INTSTS_CAPDATOF_Pos (5)
7849#define TIMER_INTSTS_CAPDATOF_Msk (0x1ul << TIMER_INTSTS_CAPDATOF_Pos)
7851#define TIMER_INTSTS_CAPFEDF_Pos (6)
7852#define TIMER_INTSTS_CAPFEDF_Msk (0x1ul << TIMER_INTSTS_CAPFEDF_Pos)
7854#define TIMER_CNT_CNT_Pos (0)
7855#define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos)
7857#define TIMER_CNT_RSTACT_Pos (31)
7858#define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos)
7860#define TIMER_CAP_CAPDAT_Pos (0)
7861#define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos)
7863#define TIMER_ECTL_EVNTDPCNT_Pos (24)
7864#define TIMER_ECTL_EVNTDPCNT_Msk (0xfful << TIMER_ECTL_EVNTDPCNT_Pos) /* TMR_CONST */ /* end of TMR register group */
7868
7869
7870/*---------------------- Pulse Width Modulation Controller -------------------------*/
7876typedef struct
7877{
7878
7879
8931 __IO uint32_t CTL0;
8932 __IO uint32_t CTL1;
8934 __I uint32_t RESERVE0[2];
8936 __IO uint32_t CLKSRC;
8937 __IO uint32_t CLKPSC0_1;
8938 __IO uint32_t CLKPSC2_3;
8939 __IO uint32_t CLKPSC4_5;
8940 __IO uint32_t CNTEN;
8941 __IO uint32_t CNTCLR;
8943 __I uint32_t RESERVE1[2];
8945 __IO uint32_t PERIOD[6];
8947 __I uint32_t RESERVE4[2];
8949 __IO uint32_t CMPDAT[6];
8951 __I uint32_t RESERVE5[2];
8953 __IO uint32_t DTCTL0_1;
8954 __IO uint32_t DTCTL2_3;
8955 __IO uint32_t DTCTL4_5;
8957 __I uint32_t RESERVE6[5];
8959 __I uint32_t CNT[6];
8961 __I uint32_t RESERVE9[2];
8963 __IO uint32_t WGCTL0;
8964 __IO uint32_t WGCTL1;
8965 __IO uint32_t MSKEN;
8966 __IO uint32_t MSK;
8967 __IO uint32_t BNF;
8968 __IO uint32_t FAILBRK;
8969 __IO uint32_t BRKCTL0_1;
8970 __IO uint32_t BRKCTL2_3;
8971 __IO uint32_t BRKCTL4_5;
8972 __IO uint32_t POLCTL;
8973 __IO uint32_t POEN;
8974 __O uint32_t SWBRK;
8975 __IO uint32_t INTEN0;
8976 __IO uint32_t INTEN1;
8977 __IO uint32_t INTSTS0;
8978 __IO uint32_t INTSTS1;
8980 __I uint32_t RESERVE10[2];
8982 __IO uint32_t ADCTS0;
8983 __IO uint32_t ADCTS1;
8985 __I uint32_t RESERVE11[8];
8987 __IO uint32_t STATUS;
8989 __I uint32_t RESERVE12[55];
8991 __IO uint32_t CAPINEN;
8992 __IO uint32_t CAPCTL;
8993 __I uint32_t CAPSTS;
8994 __I uint32_t RCAPDAT0;
8995 __I uint32_t FCAPDAT0;
8996 __I uint32_t RCAPDAT1;
8997 __I uint32_t FCAPDAT1;
8998 __I uint32_t RCAPDAT2;
8999 __I uint32_t FCAPDAT2;
9000 __I uint32_t RCAPDAT3;
9001 __I uint32_t FCAPDAT3;
9002 __I uint32_t RCAPDAT4;
9003 __I uint32_t FCAPDAT4;
9004 __I uint32_t RCAPDAT5;
9005 __I uint32_t FCAPDAT5;
9007 __I uint32_t RESERVE13[5];
9009 __IO uint32_t CAPIEN;
9010 __IO uint32_t CAPIF;
9012 __I uint32_t RESERVE14[42];
9014 __IO uint32_t SELFTEST;
9015 __I uint32_t PBUF0;
9017 __I uint32_t RESERVE15[1];
9019 __I uint32_t PBUF2;
9021 __I uint32_t RESERVE16[1];
9023 __I uint32_t PBUF4;
9025 __I uint32_t RESERVE17[1];
9027 __I uint32_t CMPBUF0;
9028 __I uint32_t CMPBUF1;
9029 __I uint32_t CMPBUF2;
9030 __I uint32_t CMPBUF3;
9031 __I uint32_t CMPBUF4;
9032 __I uint32_t CMPBUF5;
9034} PWM_T;
9035
9041#define PWM_CTL0_CTRLDn_Pos (0)
9042#define PWM_CTL0_CTRLDn_Msk (0x3ful << PWM_CTL0_CTRLDn_Pos)
9044#define PWM_CTL0_IMMLDENn_Pos (16)
9045#define PWM_CTL0_IMMLDENn_Msk (0x3ful << PWM_CTL0_IMMLDENn_Pos)
9047#define PWM_CTL0_DBGHALT_Pos (30)
9048#define PWM_CTL0_DBGHALT_Msk (0x1ul << PWM_CTL0_DBGHALT_Pos)
9050#define PWM_CTL0_DBGTRIOFF_Pos (31)
9051#define PWM_CTL0_DBGTRIOFF_Msk (0x1ul << PWM_CTL0_DBGTRIOFF_Pos)
9053#define PWM_CTL1_CNTTYPE0_Pos (0)
9054#define PWM_CTL1_CNTTYPE0_Msk (0x3ul << PWM_CTL1_CNTTYPE0_Pos)
9056#define PWM_CTL1_CNTTYPE2_Pos (4)
9057#define PWM_CTL1_CNTTYPE2_Msk (0x3ul << PWM_CTL1_CNTTYPE2_Pos)
9059#define PWM_CTL1_CNTTYPE4_Pos (8)
9060#define PWM_CTL1_CNTTYPE4_Msk (0x3ul << PWM_CTL1_CNTTYPE4_Pos)
9062#define PWM_CTL1_PWMMODEn_Pos (24)
9063#define PWM_CTL1_PWMMODEn_Msk (0x7ul << PWM_CTL1_PWMMODEn_Pos)
9065#define PWM_CLKSRC_ECLKSRC0_Pos (0)
9066#define PWM_CLKSRC_ECLKSRC0_Msk (0x7ul << PWM_CLKSRC_ECLKSRC0_Pos)
9068#define PWM_CLKSRC_ECLKSRC2_Pos (8)
9069#define PWM_CLKSRC_ECLKSRC2_Msk (0x7ul << PWM_CLKSRC_ECLKSRC2_Pos)
9071#define PWM_CLKSRC_ECLKSRC4_Pos (16)
9072#define PWM_CLKSRC_ECLKSRC4_Msk (0x7ul << PWM_CLKSRC_ECLKSRC4_Pos)
9074#define PWM_CLKPSC0_1_CLKPSC_Pos (0)
9075#define PWM_CLKPSC0_1_CLKPSC_Msk (0xffful << PWM_CLKPSC0_1_CLKPSC_Pos)
9077#define PWM_CLKPSC2_3_CLKPSC_Pos (0)
9078#define PWM_CLKPSC2_3_CLKPSC_Msk (0xffful << PWM_CLKPSC2_3_CLKPSC_Pos)
9080#define PWM_CLKPSC4_5_CLKPSC_Pos (0)
9081#define PWM_CLKPSC4_5_CLKPSC_Msk (0xffful << PWM_CLKPSC4_5_CLKPSC_Pos)
9083#define PWM_CNTEN_CNTEN0_Pos (0)
9084#define PWM_CNTEN_CNTEN0_Msk (0x1ul << PWM_CNTEN_CNTEN0_Pos)
9086#define PWM_CNTEN_CNTEN2_Pos (2)
9087#define PWM_CNTEN_CNTEN2_Msk (0x1ul << PWM_CNTEN_CNTEN2_Pos)
9089#define PWM_CNTEN_CNTEN4_Pos (4)
9090#define PWM_CNTEN_CNTEN4_Msk (0x1ul << PWM_CNTEN_CNTEN4_Pos)
9092#define PWM_CNTCLR_CNTCLR0_Pos (0)
9093#define PWM_CNTCLR_CNTCLR0_Msk (0x1ul << PWM_CNTCLR_CNTCLR0_Pos)
9095#define PWM_CNTCLR_CNTCLR2_Pos (2)
9096#define PWM_CNTCLR_CNTCLR2_Msk (0x1ul << PWM_CNTCLR_CNTCLR2_Pos)
9098#define PWM_CNTCLR_CNTCLR4_Pos (4)
9099#define PWM_CNTCLR_CNTCLR4_Msk (0x1ul << PWM_CNTCLR_CNTCLR4_Pos)
9101#define PWM_PERIOD0_PERIOD_Pos (0)
9102#define PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos)
9104#define PWM_CMPDAT0_CMPDAT_Pos (0)
9105#define PWM_CMPDAT0_CMPDAT_Msk (0xfffful << PWM_CMPDAT0_CMPDAT_Pos)
9107#define PWM_DTCTL0_1_DTCNT_Pos (0)
9108#define PWM_DTCTL0_1_DTCNT_Msk (0xffful << PWM_DTCTL0_1_DTCNT_Pos)
9110#define PWM_DTCTL0_1_DTEN_Pos (16)
9111#define PWM_DTCTL0_1_DTEN_Msk (0x1ul << PWM_DTCTL0_1_DTEN_Pos)
9113#define PWM_DTCTL0_1_DTCKSEL_Pos (24)
9114#define PWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << PWM_DTCTL0_1_DTCKSEL_Pos)
9116#define PWM_DTCTL2_3_DTCNT_Pos (0)
9117#define PWM_DTCTL2_3_DTCNT_Msk (0xffful << PWM_DTCTL2_3_DTCNT_Pos)
9119#define PWM_DTCTL2_3_DTEN_Pos (16)
9120#define PWM_DTCTL2_3_DTEN_Msk (0x1ul << PWM_DTCTL2_3_DTEN_Pos)
9122#define PWM_DTCTL2_3_DTCKSEL_Pos (24)
9123#define PWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << PWM_DTCTL2_3_DTCKSEL_Pos)
9125#define PWM_DTCTL4_5_DTCNT_Pos (0)
9126#define PWM_DTCTL4_5_DTCNT_Msk (0xffful << PWM_DTCTL4_5_DTCNT_Pos)
9128#define PWM_DTCTL4_5_DTEN_Pos (16)
9129#define PWM_DTCTL4_5_DTEN_Msk (0x1ul << PWM_DTCTL4_5_DTEN_Pos)
9131#define PWM_DTCTL4_5_DTCKSEL_Pos (24)
9132#define PWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << PWM_DTCTL4_5_DTCKSEL_Pos)
9134#define PWM_CNT0_CNT_Pos (0)
9135#define PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos)
9137#define PWM_CNT0_DIRF_Pos (16)
9138#define PWM_CNT0_DIRF_Msk (0x1ul << PWM_CNT0_DIRF_Pos)
9140#define PWM_WGCTL0_ZPCTLn_Pos (0)
9141#define PWM_WGCTL0_ZPCTLn_Msk (0xffful << PWM_WGCTL0_ZPCTLn_Pos)
9143#define PWM_WGCTL0_PRDPCTLn_Pos (16)
9144#define PWM_WGCTL0_PRDPCTLn_Msk (0xffful << PWM_WGCTL0_PRDPCTLn_Pos)
9146#define PWM_WGCTL1_CMPUCTLn_Pos (0)
9147#define PWM_WGCTL1_CMPUCTLn_Msk (0xffful << PWM_WGCTL1_CMPUCTLn_Pos)
9149#define PWM_WGCTL1_CMPDCTLn_Pos (16)
9150#define PWM_WGCTL1_CMPDCTLn_Msk (0xffful << PWM_WGCTL1_CMPDCTLn_Pos)
9152#define PWM_MSKEN_MSKENn_Pos (0)
9153#define PWM_MSKEN_MSKENn_Msk (0x3ful << PWM_MSKEN_MSKENn_Pos)
9155#define PWM_MSK_MSKDATn_Pos (0)
9156#define PWM_MSK_MSKDATn_Msk (0x3ful << PWM_MSK_MSKDATn_Pos)
9158#define PWM_BNF_BRK0FEN_Pos (0)
9159#define PWM_BNF_BRK0FEN_Msk (0x1ul << PWM_BNF_BRK0FEN_Pos)
9161#define PWM_BNF_BRK0FCS_Pos (1)
9162#define PWM_BNF_BRK0FCS_Msk (0x7ul << PWM_BNF_BRK0FCS_Pos)
9164#define PWM_BNF_BRK0FCNT_Pos (4)
9165#define PWM_BNF_BRK0FCNT_Msk (0x7ul << PWM_BNF_BRK0FCNT_Pos)
9167#define PWM_BNF_BRK0PINV_Pos (7)
9168#define PWM_BNF_BRK0PINV_Msk (0x1ul << PWM_BNF_BRK0PINV_Pos)
9170#define PWM_BNF_BRK1FEN_Pos (8)
9171#define PWM_BNF_BRK1FEN_Msk (0x1ul << PWM_BNF_BRK1FEN_Pos)
9173#define PWM_BNF_BRK1FCS_Pos (9)
9174#define PWM_BNF_BRK1FCS_Msk (0x7ul << PWM_BNF_BRK1FCS_Pos)
9176#define PWM_BNF_BRK1FCNT_Pos (12)
9177#define PWM_BNF_BRK1FCNT_Msk (0x7ul << PWM_BNF_BRK1FCNT_Pos)
9179#define PWM_BNF_BRK1PINV_Pos (15)
9180#define PWM_BNF_BRK1PINV_Msk (0x1ul << PWM_BNF_BRK1PINV_Pos)
9182#define PWM_BNF_BK0SRC_Pos (16)
9183#define PWM_BNF_BK0SRC_Msk (0x1ul << PWM_BNF_BK0SRC_Pos)
9185#define PWM_BNF_BK1SRC_Pos (24)
9186#define PWM_BNF_BK1SRC_Msk (0x1ul << PWM_BNF_BK1SRC_Pos)
9188#define PWM_FAILBRK_BODBRKEN_Pos (1)
9189#define PWM_FAILBRK_BODBRKEN_Msk (0x1ul << PWM_FAILBRK_BODBRKEN_Pos)
9191#define PWM_FAILBRK_CORBRKEN_Pos (3)
9192#define PWM_FAILBRK_CORBRKEN_Msk (0x1ul << PWM_FAILBRK_CORBRKEN_Pos)
9194#define PWM_BRKCTL0_1_BRKP0EEN_Pos (4)
9195#define PWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0EEN_Pos)
9197#define PWM_BRKCTL0_1_BRKP1EEN_Pos (5)
9198#define PWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1EEN_Pos)
9200#define PWM_BRKCTL0_1_SYSEEN_Pos (7)
9201#define PWM_BRKCTL0_1_SYSEEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSEEN_Pos)
9203#define PWM_BRKCTL0_1_BRKP0LEN_Pos (12)
9204#define PWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP0LEN_Pos)
9206#define PWM_BRKCTL0_1_BRKP1LEN_Pos (13)
9207#define PWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL0_1_BRKP1LEN_Pos)
9209#define PWM_BRKCTL0_1_SYSLEN_Pos (15)
9210#define PWM_BRKCTL0_1_SYSLEN_Msk (0x1ul << PWM_BRKCTL0_1_SYSLEN_Pos)
9212#define PWM_BRKCTL0_1_BRKAEVEN_Pos (16)
9213#define PWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL0_1_BRKAEVEN_Pos)
9215#define PWM_BRKCTL0_1_BRKAODD_Pos (18)
9216#define PWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << PWM_BRKCTL0_1_BRKAODD_Pos)
9218#define PWM_BRKCTL2_3_BRKP0EEN_Pos (4)
9219#define PWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0EEN_Pos)
9221#define PWM_BRKCTL2_3_BRKP1EEN_Pos (5)
9222#define PWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1EEN_Pos)
9224#define PWM_BRKCTL2_3_SYSEEN_Pos (7)
9225#define PWM_BRKCTL2_3_SYSEEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSEEN_Pos)
9227#define PWM_BRKCTL2_3_BRKP0LEN_Pos (12)
9228#define PWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP0LEN_Pos)
9230#define PWM_BRKCTL2_3_BRKP1LEN_Pos (13)
9231#define PWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL2_3_BRKP1LEN_Pos)
9233#define PWM_BRKCTL2_3_SYSLEN_Pos (15)
9234#define PWM_BRKCTL2_3_SYSLEN_Msk (0x1ul << PWM_BRKCTL2_3_SYSLEN_Pos)
9236#define PWM_BRKCTL2_3_BRKAEVEN_Pos (16)
9237#define PWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL2_3_BRKAEVEN_Pos)
9239#define PWM_BRKCTL2_3_BRKAODD_Pos (18)
9240#define PWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << PWM_BRKCTL2_3_BRKAODD_Pos)
9242#define PWM_BRKCTL4_5_BRKP0EEN_Pos (4)
9243#define PWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0EEN_Pos)
9245#define PWM_BRKCTL4_5_BRKP1EEN_Pos (5)
9246#define PWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1EEN_Pos)
9248#define PWM_BRKCTL4_5_SYSEEN_Pos (7)
9249#define PWM_BRKCTL4_5_SYSEEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSEEN_Pos)
9251#define PWM_BRKCTL4_5_BRKP0LEN_Pos (12)
9252#define PWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP0LEN_Pos)
9254#define PWM_BRKCTL4_5_BRKP1LEN_Pos (13)
9255#define PWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << PWM_BRKCTL4_5_BRKP1LEN_Pos)
9257#define PWM_BRKCTL4_5_SYSLEN_Pos (15)
9258#define PWM_BRKCTL4_5_SYSLEN_Msk (0x1ul << PWM_BRKCTL4_5_SYSLEN_Pos)
9260#define PWM_BRKCTL4_5_BRKAEVEN_Pos (16)
9261#define PWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << PWM_BRKCTL4_5_BRKAEVEN_Pos)
9263#define PWM_BRKCTL4_5_BRKAODD_Pos (18)
9264#define PWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << PWM_BRKCTL4_5_BRKAODD_Pos)
9266#define PWM_POLCTL_PINVn_Pos (0)
9267#define PWM_POLCTL_PINVn_Msk (0x3ful << PWM_POLCTL_PINVn_Pos)
9269#define PWM_POEN_POENn_Pos (0)
9270#define PWM_POEN_POENn_Msk (0x3ful << PWM_POEN_POENn_Pos)
9272#define PWM_SWBRK_BRKETRGn_Pos (0)
9273#define PWM_SWBRK_BRKETRGn_Msk (0x7ul << PWM_SWBRK_BRKETRGn_Pos)
9275#define PWM_SWBRK_BRKLTRGn_Pos (8)
9276#define PWM_SWBRK_BRKLTRGn_Msk (0x7ul << PWM_SWBRK_BRKLTRGn_Pos)
9278#define PWM_INTEN0_ZIEN0_Pos (0)
9279#define PWM_INTEN0_ZIEN0_Msk (0x1ul << PWM_INTEN0_ZIEN0_Pos)
9281#define PWM_INTEN0_ZIEN2_Pos (2)
9282#define PWM_INTEN0_ZIEN2_Msk (0x1ul << PWM_INTEN0_ZIEN2_Pos)
9284#define PWM_INTEN0_ZIEN4_Pos (4)
9285#define PWM_INTEN0_ZIEN4_Msk (0x1ul << PWM_INTEN0_ZIEN4_Pos)
9287#define PWM_INTEN0_PIEN0_Pos (8)
9288#define PWM_INTEN0_PIEN0_Msk (0x1ul << PWM_INTEN0_PIEN0_Pos)
9290#define PWM_INTEN0_PIEN2_Pos (10)
9291#define PWM_INTEN0_PIEN2_Msk (0x1ul << PWM_INTEN0_PIEN2_Pos)
9293#define PWM_INTEN0_PIEN4_Pos (12)
9294#define PWM_INTEN0_PIEN4_Msk (0x1ul << PWM_INTEN0_PIEN4_Pos)
9296#define PWM_INTEN0_CMPUIENn_Pos (16)
9297#define PWM_INTEN0_CMPUIENn_Msk (0x3ful << PWM_INTEN0_CMPUIENn_Pos)
9299#define PWM_INTEN0_CMPDIENn_Pos (24)
9300#define PWM_INTEN0_CMPDIENn_Msk (0x3ful << PWM_INTEN0_CMPDIENn_Pos)
9302#define PWM_INTEN1_BRKEIEN0_1_Pos (0)
9303#define PWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKEIEN0_1_Pos)
9305#define PWM_INTEN1_BRKEIEN2_3_Pos (1)
9306#define PWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKEIEN2_3_Pos)
9308#define PWM_INTEN1_BRKEIEN4_5_Pos (2)
9309#define PWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKEIEN4_5_Pos)
9311#define PWM_INTEN1_BRKLIEN0_1_Pos (8)
9312#define PWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << PWM_INTEN1_BRKLIEN0_1_Pos)
9314#define PWM_INTEN1_BRKLIEN2_3_Pos (9)
9315#define PWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << PWM_INTEN1_BRKLIEN2_3_Pos)
9317#define PWM_INTEN1_BRKLIEN4_5_Pos (10)
9318#define PWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << PWM_INTEN1_BRKLIEN4_5_Pos)
9320#define PWM_INTSTS0_ZIF0_Pos (0)
9321#define PWM_INTSTS0_ZIF0_Msk (0x1ul << PWM_INTSTS0_ZIF0_Pos)
9323#define PWM_INTSTS0_ZIF2_Pos (2)
9324#define PWM_INTSTS0_ZIF2_Msk (0x1ul << PWM_INTSTS0_ZIF2_Pos)
9326#define PWM_INTSTS0_ZIF4_Pos (4)
9327#define PWM_INTSTS0_ZIF4_Msk (0x1ul << PWM_INTSTS0_ZIF4_Pos)
9329#define PWM_INTSTS0_PIF0_Pos (8)
9330#define PWM_INTSTS0_PIF0_Msk (0x1ul << PWM_INTSTS0_PIF0_Pos)
9332#define PWM_INTSTS0_PIF2_Pos (10)
9333#define PWM_INTSTS0_PIF2_Msk (0x1ul << PWM_INTSTS0_PIF2_Pos)
9335#define PWM_INTSTS0_PIF4_Pos (12)
9336#define PWM_INTSTS0_PIF4_Msk (0x1ul << PWM_INTSTS0_PIF4_Pos)
9338#define PWM_INTSTS0_CMPUIFn_Pos (16)
9339#define PWM_INTSTS0_CMPUIFn_Msk (0x3ful << PWM_INTSTS0_CMPUIFn_Pos)
9341#define PWM_INTSTS0_CMPDIFn_Pos (24)
9342#define PWM_INTSTS0_CMPDIFn_Msk (0x3ful << PWM_INTSTS0_CMPDIFn_Pos)
9344#define PWM_INTSTS1_BRKEIF0_Pos (0)
9345#define PWM_INTSTS1_BRKEIF0_Msk (0x1ul << PWM_INTSTS1_BRKEIF0_Pos)
9347#define PWM_INTSTS1_BRKEIF1_Pos (1)
9348#define PWM_INTSTS1_BRKEIF1_Msk (0x1ul << PWM_INTSTS1_BRKEIF1_Pos)
9350#define PWM_INTSTS1_BRKEIF2_Pos (2)
9351#define PWM_INTSTS1_BRKEIF2_Msk (0x1ul << PWM_INTSTS1_BRKEIF2_Pos)
9353#define PWM_INTSTS1_BRKEIF3_Pos (3)
9354#define PWM_INTSTS1_BRKEIF3_Msk (0x1ul << PWM_INTSTS1_BRKEIF3_Pos)
9356#define PWM_INTSTS1_BRKEIF4_Pos (4)
9357#define PWM_INTSTS1_BRKEIF4_Msk (0x1ul << PWM_INTSTS1_BRKEIF4_Pos)
9359#define PWM_INTSTS1_BRKEIF5_Pos (5)
9360#define PWM_INTSTS1_BRKEIF5_Msk (0x1ul << PWM_INTSTS1_BRKEIF5_Pos)
9362#define PWM_INTSTS1_BRKLIF0_Pos (8)
9363#define PWM_INTSTS1_BRKLIF0_Msk (0x1ul << PWM_INTSTS1_BRKLIF0_Pos)
9365#define PWM_INTSTS1_BRKLIF1_Pos (9)
9366#define PWM_INTSTS1_BRKLIF1_Msk (0x1ul << PWM_INTSTS1_BRKLIF1_Pos)
9368#define PWM_INTSTS1_BRKLIF2_Pos (10)
9369#define PWM_INTSTS1_BRKLIF2_Msk (0x1ul << PWM_INTSTS1_BRKLIF2_Pos)
9371#define PWM_INTSTS1_BRKLIF3_Pos (11)
9372#define PWM_INTSTS1_BRKLIF3_Msk (0x1ul << PWM_INTSTS1_BRKLIF3_Pos)
9374#define PWM_INTSTS1_BRKLIF4_Pos (12)
9375#define PWM_INTSTS1_BRKLIF4_Msk (0x1ul << PWM_INTSTS1_BRKLIF4_Pos)
9377#define PWM_INTSTS1_BRKLIF5_Pos (13)
9378#define PWM_INTSTS1_BRKLIF5_Msk (0x1ul << PWM_INTSTS1_BRKLIF5_Pos)
9380#define PWM_INTSTS1_BRKESTS0_Pos (16)
9381#define PWM_INTSTS1_BRKESTS0_Msk (0x1ul << PWM_INTSTS1_BRKESTS0_Pos)
9383#define PWM_INTSTS1_BRKESTS1_Pos (17)
9384#define PWM_INTSTS1_BRKESTS1_Msk (0x1ul << PWM_INTSTS1_BRKESTS1_Pos)
9386#define PWM_INTSTS1_BRKESTS2_Pos (18)
9387#define PWM_INTSTS1_BRKESTS2_Msk (0x1ul << PWM_INTSTS1_BRKESTS2_Pos)
9389#define PWM_INTSTS1_BRKESTS3_Pos (19)
9390#define PWM_INTSTS1_BRKESTS3_Msk (0x1ul << PWM_INTSTS1_BRKESTS3_Pos)
9392#define PWM_INTSTS1_BRKESTS4_Pos (20)
9393#define PWM_INTSTS1_BRKESTS4_Msk (0x1ul << PWM_INTSTS1_BRKESTS4_Pos)
9395#define PWM_INTSTS1_BRKESTS5_Pos (21)
9396#define PWM_INTSTS1_BRKESTS5_Msk (0x1ul << PWM_INTSTS1_BRKESTS5_Pos)
9398#define PWM_INTSTS1_BRKLSTS0_Pos (24)
9399#define PWM_INTSTS1_BRKLSTS0_Msk (0x1ul << PWM_INTSTS1_BRKLSTS0_Pos)
9401#define PWM_INTSTS1_BRKLSTS1_Pos (25)
9402#define PWM_INTSTS1_BRKLSTS1_Msk (0x1ul << PWM_INTSTS1_BRKLSTS1_Pos)
9404#define PWM_INTSTS1_BRKLSTS2_Pos (26)
9405#define PWM_INTSTS1_BRKLSTS2_Msk (0x1ul << PWM_INTSTS1_BRKLSTS2_Pos)
9407#define PWM_INTSTS1_BRKLSTS3_Pos (27)
9408#define PWM_INTSTS1_BRKLSTS3_Msk (0x1ul << PWM_INTSTS1_BRKLSTS3_Pos)
9410#define PWM_INTSTS1_BRKLSTS4_Pos (28)
9411#define PWM_INTSTS1_BRKLSTS4_Msk (0x1ul << PWM_INTSTS1_BRKLSTS4_Pos)
9413#define PWM_INTSTS1_BRKLSTS5_Pos (29)
9414#define PWM_INTSTS1_BRKLSTS5_Msk (0x1ul << PWM_INTSTS1_BRKLSTS5_Pos)
9416#define PWM_ADCTS0_TRGSEL0_Pos (0)
9417#define PWM_ADCTS0_TRGSEL0_Msk (0xful << PWM_ADCTS0_TRGSEL0_Pos)
9419#define PWM_ADCTS0_TRGEN0_Pos (7)
9420#define PWM_ADCTS0_TRGEN0_Msk (0x1ul << PWM_ADCTS0_TRGEN0_Pos)
9422#define PWM_ADCTS0_TRGSEL1_Pos (8)
9423#define PWM_ADCTS0_TRGSEL1_Msk (0xful << PWM_ADCTS0_TRGSEL1_Pos)
9425#define PWM_ADCTS0_TRGEN1_Pos (15)
9426#define PWM_ADCTS0_TRGEN1_Msk (0x1ul << PWM_ADCTS0_TRGEN1_Pos)
9428#define PWM_ADCTS0_TRGSEL2_Pos (16)
9429#define PWM_ADCTS0_TRGSEL2_Msk (0xful << PWM_ADCTS0_TRGSEL2_Pos)
9431#define PWM_ADCTS0_TRGEN2_Pos (23)
9432#define PWM_ADCTS0_TRGEN2_Msk (0x1ul << PWM_ADCTS0_TRGEN2_Pos)
9434#define PWM_ADCTS0_TRGSEL3_Pos (24)
9435#define PWM_ADCTS0_TRGSEL3_Msk (0xful << PWM_ADCTS0_TRGSEL3_Pos)
9437#define PWM_ADCTS0_TRGEN3_Pos (31)
9438#define PWM_ADCTS0_TRGEN3_Msk (0x1ul << PWM_ADCTS0_TRGEN3_Pos)
9440#define PWM_ADCTS1_TRGSEL4_Pos (0)
9441#define PWM_ADCTS1_TRGSEL4_Msk (0xful << PWM_ADCTS1_TRGSEL4_Pos)
9443#define PWM_ADCTS1_TRGEN4_Pos (7)
9444#define PWM_ADCTS1_TRGEN4_Msk (0x1ul << PWM_ADCTS1_TRGEN4_Pos)
9446#define PWM_ADCTS1_TRGSEL5_Pos (8)
9447#define PWM_ADCTS1_TRGSEL5_Msk (0xful << PWM_ADCTS1_TRGSEL5_Pos)
9449#define PWM_ADCTS1_TRGEN5_Pos (15)
9450#define PWM_ADCTS1_TRGEN5_Msk (0x1ul << PWM_ADCTS1_TRGEN5_Pos)
9452#define PWM_STATUS_CNTMAX0_Pos (0)
9453#define PWM_STATUS_CNTMAX0_Msk (0x1ul << PWM_STATUS_CNTMAX0_Pos)
9455#define PWM_STATUS_CNTMAX2_Pos (2)
9456#define PWM_STATUS_CNTMAX2_Msk (0x1ul << PWM_STATUS_CNTMAX2_Pos)
9458#define PWM_STATUS_CNTMAX4_Pos (4)
9459#define PWM_STATUS_CNTMAX4_Msk (0x1ul << PWM_STATUS_CNTMAX4_Pos)
9461#define PWM_STATUS_ADCTRGn_Pos (16)
9462#define PWM_STATUS_ADCTRGn_Msk (0x3ful << PWM_STATUS_ADCTRGn_Pos)
9464#define PWM_CAPINEN_CAPINENn_Pos (0)
9465#define PWM_CAPINEN_CAPINENn_Msk (0x3ful << PWM_CAPINEN_CAPINENn_Pos)
9467#define PWM_CAPCTL_CAPENn_Pos (0)
9468#define PWM_CAPCTL_CAPENn_Msk (0x3ful << PWM_CAPCTL_CAPENn_Pos)
9470#define PWM_CAPCTL_CAPINVn_Pos (8)
9471#define PWM_CAPCTL_CAPINVn_Msk (0x3ful << PWM_CAPCTL_CAPINVn_Pos)
9473#define PWM_CAPCTL_RCRLDENn_Pos (16)
9474#define PWM_CAPCTL_RCRLDENn_Msk (0x3ful << PWM_CAPCTL_RCRLDENn_Pos)
9476#define PWM_CAPCTL_FCRLDENn_Pos (24)
9477#define PWM_CAPCTL_FCRLDENn_Msk (0x3ful << PWM_CAPCTL_FCRLDENn_Pos)
9479#define PWM_CAPSTS_CRIFOVn_Pos (0)
9480#define PWM_CAPSTS_CRIFOVn_Msk (0x3ful << PWM_CAPSTS_CRIFOVn_Pos)
9482#define PWM_CAPSTS_CFIFOVn_Pos (8)
9483#define PWM_CAPSTS_CFIFOVn_Msk (0x3ful << PWM_CAPSTS_CFIFOVn_Pos)
9485#define PWM_RCAPDAT0_RCAPDAT_Pos (0)
9486#define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos)
9488#define PWM_FCAPDAT0_FCAPDAT_Pos (0)
9489#define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos)
9491#define PWM_RCAPDAT1_RCAPDAT_Pos (0)
9492#define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos)
9494#define PWM_FCAPDAT1_FCAPDAT_Pos (0)
9495#define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos)
9497#define PWM_RCAPDAT2_RCAPDAT_Pos (0)
9498#define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos)
9500#define PWM_FCAPDAT2_FCAPDAT_Pos (0)
9501#define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos)
9503#define PWM_RCAPDAT3_RCAPDAT_Pos (0)
9504#define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos)
9506#define PWM_FCAPDAT3_FCAPDAT_Pos (0)
9507#define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos)
9509#define PWM_RCAPDAT4_RCAPDAT_Pos (0)
9510#define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos)
9512#define PWM_FCAPDAT4_FCAPDAT_Pos (0)
9513#define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos)
9515#define PWM_RCAPDAT5_RCAPDAT_Pos (0)
9516#define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos)
9518#define PWM_FCAPDAT5_FCAPDAT_Pos (0)
9519#define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos)
9521#define PWM_CAPIEN_CAPRIENn_Pos (0)
9522#define PWM_CAPIEN_CAPRIENn_Msk (0x3ful << PWM_CAPIEN_CAPRIENn_Pos)
9524#define PWM_CAPIEN_CAPFIENn_Pos (8)
9525#define PWM_CAPIEN_CAPFIENn_Msk (0x3ful << PWM_CAPIEN_CAPFIENn_Pos)
9527#define PWM_CAPIF_CAPRIFn_Pos (0)
9528#define PWM_CAPIF_CAPRIFn_Msk (0x3ful << PWM_CAPIF_CAPRIFn_Pos)
9530#define PWM_CAPIF_CAPFIFn_Pos (8)
9531#define PWM_CAPIF_CAPFIFn_Msk (0x3ful << PWM_CAPIF_CAPFIFn_Pos)
9533#define PWM_PBUF0_PBUF_Pos (0)
9534#define PWM_PBUF0_PBUF_Msk (0xfffful << PWM_PBUF0_PBUF_Pos)
9536#define PWM_PBUF2_PBUF_Pos (0)
9537#define PWM_PBUF2_PBUF_Msk (0xfffful << PWM_PBUF2_PBUF_Pos)
9539#define PWM_PBUF4_PBUF_Pos (0)
9540#define PWM_PBUF4_PBUF_Msk (0xfffful << PWM_PBUF4_PBUF_Pos)
9542#define PWM_CMPBUF0_CMPBUF_Pos (0)
9543#define PWM_CMPBUF0_CMPBUF_Msk (0xfffful << PWM_CMPBUF0_CMPBUF_Pos)
9545#define PWM_CMPBUF1_CMPBUF_Pos (0)
9546#define PWM_CMPBUF1_CMPBUF_Msk (0xfffful << PWM_CMPBUF1_CMPBUF_Pos)
9548#define PWM_CMPBUF2_CMPBUF_Pos (0)
9549#define PWM_CMPBUF2_CMPBUF_Msk (0xfffful << PWM_CMPBUF2_CMPBUF_Pos)
9551#define PWM_CMPBUF3_CMPBUF_Pos (0)
9552#define PWM_CMPBUF3_CMPBUF_Msk (0xfffful << PWM_CMPBUF3_CMPBUF_Pos)
9554#define PWM_CMPBUF4_CMPBUF_Pos (0)
9555#define PWM_CMPBUF4_CMPBUF_Msk (0xfffful << PWM_CMPBUF4_CMPBUF_Pos)
9557#define PWM_CMPBUF5_CMPBUF_Pos (0)
9558#define PWM_CMPBUF5_CMPBUF_Msk (0xfffful << PWM_CMPBUF5_CMPBUF_Pos) /* PWM_CONST */ /* end of PWM register group */
9562
9563
9564/*---------------------- Watch Dog Timer Controller -------------------------*/
9570typedef struct
9571{
9572
9573
9649 __IO uint32_t CTL;
9650 __IO uint32_t INTEN;
9651 __IO uint32_t STATUS;
9653} WDT_T;
9654
9660#define WDT_CTL_RSTCNT_Pos (0)
9661#define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos)
9663#define WDT_CTL_RSTEN_Pos (1)
9664#define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos)
9666#define WDT_CTL_WKEN_Pos (2)
9667#define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos)
9669#define WDT_CTL_WDTEN_Pos (3)
9670#define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos)
9672#define WDT_CTL_WTIS_Pos (4)
9673#define WDT_CTL_WTIS_Msk (0x7ul << WDT_CTL_WTIS_Pos)
9675#define WDT_CTL_WTRDSEL_Pos (8)
9676#define WDT_CTL_WTRDSEL_Msk (0x3ul << WDT_CTL_WTRDSEL_Pos)
9678#define WDT_CTL_DBGEN_Pos (31)
9679#define WDT_CTL_DBGEN_Msk (0x1ul << WDT_CTL_DBGEN_Pos)
9681#define WDT_INTEN_WDTIE_Pos (0)
9682#define WDT_INTEN_WDTIE_Msk (0x1ul << WDT_INTEN_WDTIE_Pos)
9684#define WDT_STATUS_WDTIF_Pos (0)
9685#define WDT_STATUS_WDTIF_Msk (0x1ul << WDT_STATUS_WDTIF_Pos)
9687#define WDT_STATUS_RSTF_Pos (1)
9688#define WDT_STATUS_RSTF_Msk (0x1ul << WDT_STATUS_RSTF_Pos)
9690#define WDT_STATUS_WKF_Pos (2)
9691#define WDT_STATUS_WKF_Msk (0x1ul << WDT_STATUS_WKF_Pos) /* WDT_CONST */ /* end of WDT register group */
9695
9696
9697/*---------------------- Window Watchdog Timer -------------------------*/
9703typedef struct
9704{
9705
9706
9762 __O uint32_t RLDCNT;
9763 __IO uint32_t CTL;
9764 __IO uint32_t INTEN;
9765 __IO uint32_t STATUS;
9766 __I uint32_t CNT;
9768} WWDT_T;
9769
9775#define WWDT_RLDCNT_RLDCNT_Pos (0)
9776#define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos)
9778#define WWDT_CTL_WWDTEN_Pos (0)
9779#define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos)
9781#define WWDT_CTL_PERIODSEL_Pos (8)
9782#define WWDT_CTL_PERIODSEL_Msk (0xful << WWDT_CTL_PERIODSEL_Pos)
9784#define WWDT_CTL_WINCMP_Pos (16)
9785#define WWDT_CTL_WINCMP_Msk (0x3ful << WWDT_CTL_WINCMP_Pos)
9787#define WWDT_CTL_DBGEN_Pos (31)
9788#define WWDT_CTL_DBGEN_Msk (0x1ul << WWDT_CTL_DBGEN_Pos)
9790#define WWDT_INTEN_WWDTIE_Pos (0)
9791#define WWDT_INTEN_WWDTIE_Msk (0x1ul << WWDT_INTEN_WWDTIE_Pos)
9793#define WWDT_STATUS_WWDTIF_Pos (0)
9794#define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos)
9796#define WWDT_STATUS_WWDTRF_Pos (1)
9797#define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos)
9799#define WWDT_CNT_WWDT_CNTDAT_Pos (0)
9800#define WWDT_CNT_WWDT_CNTDAT_Msk (0x3ful << WWDT_CNT_WWDT_CNTDAT_Pos) /* WWDT_CONST */ /* end of WWDT register group */
9804
9805
9806/*---------------------- Real Time Clock Controller -------------------------*/
9812typedef struct
9813{
9814
9815
10123 __IO uint32_t INIT;
10124 __IO uint32_t RWEN;
10125 __IO uint32_t FREQADJ;
10126 __IO uint32_t TIME;
10127 __IO uint32_t CAL;
10128 __IO uint32_t CLKFMT;
10129 __IO uint32_t WEEKDAY;
10130 __IO uint32_t TALM;
10131 __IO uint32_t CALM;
10132 __I uint32_t LEAPYEAR;
10133 __IO uint32_t INTEN;
10134 __IO uint32_t INTSTS;
10135 __IO uint32_t TICK;
10136 __IO uint32_t TAMSK;
10137 __IO uint32_t CAMSK;
10138 __IO uint32_t SPRCTL;
10139 __IO uint32_t SPR[5];
10141 __I uint32_t RESERVE0[43];
10143 __IO uint32_t LXTCTL;
10144 __IO uint32_t LXTOCTL;
10145 __IO uint32_t LXTICTL;
10146 __IO uint32_t TAMPCTL;
10148 __I uint32_t RESERVE1[56];
10150 __IO uint32_t MISCCTL;
10151} RTC_T;
10152
10158#define RTC_INIT_INIT_ACTIVE_Pos (0)
10159#define RTC_INIT_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_INIT_ACTIVE_Pos)
10161#define RTC_INIT_INIT_Pos (1)
10162#define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos)
10164#define RTC_RWEN_RWEN_Pos (0)
10165#define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos)
10167#define RTC_RWEN_RWENF_Pos (16)
10168#define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos)
10170#define RTC_RWEN_RTCBUSY_Pos (24)
10171#define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos)
10173#define RTC_FREQADJ_FREQADJ_Pos (0)
10174#define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FCR_FCR_Pos)
10176#define RTC_TIME_SEC_Pos (0)
10177#define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos)
10179#define RTC_TIME_TENSEC_Pos (4)
10180#define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos)
10182#define RTC_TIME_MIN_Pos (8)
10183#define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos)
10185#define RTC_TIME_TENMIN_Pos (12)
10186#define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos)
10188#define RTC_TIME_HR_Pos (16)
10189#define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos)
10191#define RTC_TIME_TENHR_Pos (20)
10192#define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos)
10194#define RTC_CAL_DAY_Pos (0)
10195#define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos)
10197#define RTC_CAL_TENDAY_Pos (4)
10198#define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos)
10200#define RTC_CAL_MON_Pos (8)
10201#define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos)
10203#define RTC_CAL_TENMON_Pos (12)
10204#define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos)
10206#define RTC_CAL_YEAR_Pos (16)
10207#define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos)
10209#define RTC_CAL_TENYEAR_Pos (20)
10210#define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos)
10212#define RTC_CLKFMT_24HEN_Pos (0)
10213#define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos)
10215#define RTC_WEEKDAY_WEEKDAY_Pos (0)
10216#define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos)
10218#define RTC_TALM_SEC_Pos (0)
10219#define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos)
10221#define RTC_TALM_TENSEC_Pos (4)
10222#define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos)
10224#define RTC_TALM_MIN_Pos (8)
10225#define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos)
10227#define RTC_TALM_TENMIN_Pos (12)
10228#define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos)
10230#define RTC_TALM_HR_Pos (16)
10231#define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos)
10233#define RTC_TALM_TENHR_Pos (20)
10234#define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos)
10236#define RTC_CALM_DAY_Pos (0)
10237#define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos)
10239#define RTC_CALM_TENDAY_Pos (4)
10240#define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos)
10242#define RTC_CALM_MON_Pos (8)
10243#define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos)
10245#define RTC_CALM_TENMON_Pos (12)
10246#define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos)
10248#define RTC_CALM_YEAR_Pos (16)
10249#define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos)
10251#define RTC_CALM_TENYEAR_Pos (20)
10252#define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos)
10254#define RTC_LEAPYEAR_LEAPYEAR_Pos (0)
10255#define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos)
10257#define RTC_INTEN_ALMIEN_Pos (0)
10258#define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos)
10260#define RTC_INTEN_TICKIEN_Pos (1)
10261#define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos)
10263#define RTC_INTEN_SNPDIEN_Pos (2)
10264#define RTC_INTEN_SNPDIEN_Msk (0x1ul << RTC_INTEN_SNPDIEN_Pos)
10266#define RTC_INTSTS_ALMIF_Pos (0)
10267#define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos)
10269#define RTC_INTSTS_TICKIF_Pos (1)
10270#define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos)
10272#define RTC_INTSTS_SNPDIF_Pos (2)
10273#define RTC_INTSTS_SNPDIF_Msk (0x1ul << RTC_INTSTS_SNPDIF_Pos)
10275#define RTC_TICK_TICK_Pos (0)
10276#define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos)
10278#define RTC_TAMSK_MSEC_Pos (0)
10279#define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos)
10281#define RTC_TAMSK_MTENSEC_Pos (1)
10282#define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos)
10284#define RTC_TAMSK_MMIN_Pos (2)
10285#define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos)
10287#define RTC_TAMSK_MTENMIN_Pos (3)
10288#define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos)
10290#define RTC_TAMSK_MHR_Pos (4)
10291#define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos)
10293#define RTC_TAMSK_MTENHR_Pos (5)
10294#define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos)
10296#define RTC_CAMSK_MDAY_Pos (0)
10297#define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos)
10299#define RTC_CAMSK_MTENDAY_Pos (1)
10300#define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos)
10302#define RTC_CAMSK_MMON_Pos (2)
10303#define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos)
10305#define RTC_CAMSK_MTENMON_Pos (3)
10306#define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos)
10308#define RTC_CAMSK_MYEAR_Pos (4)
10309#define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos)
10311#define RTC_CAMSK_MTENYEAR_Pos (5)
10312#define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos)
10314#define RTC_SPRCTL_SNPDEN_Pos (0)
10315#define RTC_SPRCTL_SNPDEN_Msk (0x1ul << RTC_SPRCTL_SNPDEN_Pos)
10317#define RTC_SPRCTL_SNPTYPE0_Pos (1)
10318#define RTC_SPRCTL_SNPTYPE0_Msk (0x1ul << RTC_SPRCTL_SNPTYPE0_Pos)
10320#define RTC_SPRCTL_SPRRWEN_Pos (2)
10321#define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos)
10323#define RTC_SPRCTL_SPRCSTS_Pos (5)
10324#define RTC_SPRCTL_SPRCSTS_Msk (0x1ul << RTC_SPRCTL_SPRCSTS_Pos)
10326#define RTC_SPR0_SPARE_Pos (0)
10327#define RTC_SPR0_SPARE_Msk (0xfffffffful << RTC_SPR0_SPARE_Pos)
10329#define RTC_SPR1_SPARE_Pos (0)
10330#define RTC_SPR1_SPARE_Msk (0xfffffffful << RTC_SPR1_SPARE_Pos)
10332#define RTC_SPR2_SPARE_Pos (0)
10333#define RTC_SPR2_SPARE_Msk (0xfffffffful << RTC_SPR2_SPARE_Pos)
10335#define RTC_SPR3_SPARE_Pos (0)
10336#define RTC_SPR3_SPARE_Msk (0xfffffffful << RTC_SPR3_SPARE_Pos)
10338#define RTC_SPR4_SPARE_Pos (0)
10339#define RTC_SPR4_SPARE_Msk (0xfffffffful << RTC_SPR4_SPARE_Pos)
10341#define RTC_LXTCTL_LXT_TYPE_Pos (0)
10342#define RTC_LXTCTL_LXT_TYPE_Msk (0x1ul << RTC_LXTCTL_LXT_TYPE_Pos)
10344#define RTC_LXTOCTL_OPMODE_Pos (0)
10345#define RTC_LXTOCTL_OPMODE_Msk (0x3ul << RTC_LXTOCTL_OPMODE_Pos)
10347#define RTC_LXTOCTL_DOUT_Pos (2)
10348#define RTC_LXTOCTL_DOUT_Msk (0x1ul << RTC_LXTOCTL_DOUT_Pos)
10350#define RTC_LXTOCTL_CTLSEL_Pos (3)
10351#define RTC_LXTOCTL_CTLSEL_Msk (0x1ul << RTC_LXTOCTL_CTLSEL_Pos)
10353#define RTC_LXTICTL_OPMODE_Pos (0)
10354#define RTC_LXTICTL_OPMODE_Msk (0x3ul << RTC_LXTICTL_OPMODE_Pos)
10356#define RTC_LXTICTL_DOUT_Pos (2)
10357#define RTC_LXTICTL_DOUT_Msk (0x1ul << RTC_LXTICTL_DOUT_Pos)
10359#define RTC_LXTICTL_CTLSEL_Pos (3)
10360#define RTC_LXTICTL_CTLSEL_Msk (0x1ul << RTC_LXTICTL_CTLSEL_Pos)
10362#define RTC_TAMPCTL_OPMODE_Pos (0)
10363#define RTC_TAMPCTL_OPMODE_Msk (0x3ul << RTC_TAMPCTL_OPMODE_Pos)
10365#define RTC_TAMPCTL_DOUT_Pos (2)
10366#define RTC_TAMPCTL_DOUT_Msk (0x1ul << RTC_TAMPCTL_DOUT_Pos)
10368#define RTC_TAMPCTL_CTLSEL_Pos (3)
10369#define RTC_TAMPCTL_CTLSEL_Msk (0x1ul << RTC_TAMPCTL_CTLSEL_Pos)
10371#define RTC_MISCCTL_GAINSEL_Pos (12)
10372#define RTC_MISCCTL_GAINSEL_Msk (0x3ul << RTC_MISCCTL_GAINSEL_Pos) /* RTC_CONST */ /* end of RTC register group */
10376
10377
10378/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
10384typedef struct
10385{
10386
10387
10927 __IO uint32_t DAT;
10928 __IO uint32_t CTRL;
10929 __IO uint32_t LINE;
10930 __IO uint32_t INTEN;
10931 __IO uint32_t INTSTS;
10932 __IO uint32_t TRSR;
10933 __IO uint32_t FIFOSTS;
10934 __IO uint32_t MODEM;
10935 __IO uint32_t TOUT;
10936 __IO uint32_t BAUD;
10938 __I uint32_t RESERVE0[2];
10940 __IO uint32_t IRDA;
10941 __IO uint32_t ALTCTL;
10942 __IO uint32_t FUNCSEL;
10943 __IO uint32_t BRCOMPAT;
10944 __IO uint32_t WKUPEN;
10945 __IO uint32_t WKUPSTS;
10947} UART_T;
10948
10954#define UART_DAT_DAT_Pos (0)
10955#define UART_DAT_DAT_Msk (0xfful << UART_RBR_RBR_Pos)
10957#define UART_CTRL_RXRST_Pos (0)
10958#define UART_CTRL_RXRST_Msk (0x1ul << UART_CTRL_RXRST_Pos)
10960#define UART_CTRL_TXRST_Pos (1)
10961#define UART_CTRL_TXRST_Msk (0x1ul << UART_CTRL_TXRST_Pos)
10963#define UART_CTRL_RXOFF_Pos (2)
10964#define UART_CTRL_RXOFF_Msk (0x1ul << UART_CTRL_RXOFF_Pos)
10966#define UART_CTRL_TXOFF_Pos (3)
10967#define UART_CTRL_TXOFF_Msk (0x1ul << UART_CTRL_TXOFF_Pos)
10969#define UART_CTRL_ATORTSEN_Pos (4)
10970#define UART_CTRL_ATORTSEN_Msk (0x1ul << UART_CTRL_ATORTSEN_Pos)
10972#define UART_CTRL_ATOCTSEN_Pos (5)
10973#define UART_CTRL_ATOCTSEN_Msk (0x1ul << UART_CTRL_ATOCTSEN_Pos)
10975#define UART_CTRL_RXDMAEN_Pos (6)
10976#define UART_CTRL_RXDMAEN_Msk (0x1ul << UART_CTRL_RXDMAEN_Pos)
10978#define UART_CTRL_TXDMAEN_Pos (7)
10979#define UART_CTRL_TXDMAEN_Msk (0x1ul << UART_CTRL_TXDMAEN_Pos)
10981#define UART_CTRL_FTOEN_Pos (8)
10982#define UART_CTRL_FTOEN_Msk (0x1ul << UART_CTRL_FTOEN_Pos)
10984#define UART_CTRL_ABRDEN_Pos (12)
10985#define UART_CTRL_ABRDEN_Msk (0x1ul << UART_CTRL_ABRDEN_Pos)
10987#define UART_CTRL_ABRDBITS_Pos (13)
10988#define UART_CTRL_ABRDBITS_Msk (0x3ul << UART_CTRL_ABRDBITS_Pos)
10990#define UART_LINE_WLS_Pos (0)
10991#define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos)
10993#define UART_LINE_NSB_Pos (2)
10994#define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos)
10996#define UART_LINE_PBE_Pos (3)
10997#define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos)
10999#define UART_LINE_EPE_Pos (4)
11000#define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos)
11002#define UART_LINE_SPE_Pos (5)
11003#define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos)
11005#define UART_LINE_BCB_Pos (6)
11006#define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos)
11008#define UART_LINE_RFITL_Pos (8)
11009#define UART_LINE_RFITL_Msk (0x3ul << UART_LINE_RFITL_Pos)
11011#define UART_LINE_RTSTRGLV_Pos (12)
11012#define UART_LINE_RTSTRGLV_Msk (0x3ul << UART_LINE_RTSTRGLV_Pos)
11014#define UART_INTEN_RDAIEN_Pos (0)
11015#define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos)
11017#define UART_INTEN_THREIEN_Pos (1)
11018#define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos)
11020#define UART_INTEN_RLSIEN_Pos (2)
11021#define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos)
11023#define UART_INTEN_MODEMIEN_Pos (3)
11024#define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos)
11026#define UART_INTEN_RXTOIEN_Pos (4)
11027#define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos)
11029#define UART_INTEN_BUFERRIEN_Pos (5)
11030#define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos)
11032#define UART_INTEN_WKUPIEN_Pos (6)
11033#define UART_INTEN_WKUPIEN_Msk (0x1ul << UART_INTEN_WKUPIEN_Pos)
11035#define UART_INTEN_ABRIEN_Pos (7)
11036#define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos)
11038#define UART_INTEN_LINIEN_Pos (8)
11039#define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos)
11041#define UART_INTEN_TXENDIEN_Pos (9)
11042#define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos)
11044#define UART_INTSTS_RDAIF_Pos (0)
11045#define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos)
11047#define UART_INTSTS_THREIF_Pos (1)
11048#define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos)
11050#define UART_INTSTS_RLSIF_Pos (2)
11051#define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos)
11053#define UART_INTSTS_MODEMIF_Pos (3)
11054#define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos)
11056#define UART_INTSTS_RXTOIF_Pos (4)
11057#define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos)
11059#define UART_INTSTS_BUFERRIF_Pos (5)
11060#define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos)
11062#define UART_INTSTS_WKUPIF_Pos (6)
11063#define UART_INTSTS_WKUPIF_Msk (0x1ul << UART_INTSTS_WKUPIF_Pos)
11065#define UART_INTSTS_ABRIF_Pos (7)
11066#define UART_INTSTS_ABRIF_Msk (0x1ul << UART_INTSTS_ABRIF_Pos)
11068#define UART_INTSTS_LINIF_Pos (8)
11069#define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos)
11071#define UART_TRSR_ADDRDETF_Pos (0)
11072#define UART_TRSR_ADDRDETF_Msk (0x1ul << UART_TRSR_ADDRDETF_Pos)
11074#define UART_TRSR_ABRDIF_Pos (1)
11075#define UART_TRSR_ABRDIF_Msk (0x1ul << UART_TRSR_ABRDIF_Pos)
11077#define UART_TRSR_ABRDTOIF_Pos (2)
11078#define UART_TRSR_ABRDTOIF_Msk (0x1ul << UART_TRSR_ABRDTOIF_Pos)
11080#define UART_TRSR_LINTXIF_Pos (3)
11081#define UART_TRSR_LINTXIF_Msk (0x1ul << UART_TRSR_LINTXIF_Pos)
11083#define UART_TRSR_LINRXIF_Pos (4)
11084#define UART_TRSR_LINRXIF_Msk (0x1ul << UART_TRSR_LINRXIF_Pos)
11086#define UART_TRSR_BITEF_Pos (5)
11087#define UART_TRSR_BITEF_Msk (0x1ul << UART_TRSR_BITEF_Pos)
11089#define UART_TRSR_RXBUSY_Pos (7)
11090#define UART_TRSR_RXBUSY_Msk (0x1ul << UART_TRSR_RXBUSY_Pos)
11092#define UART_TRSR_SLVSYNCF_Pos (8)
11093#define UART_TRSR_SLVSYNCF_Msk (0x1ul << UART_TRSR_SLVSYNCF_Pos)
11095#define UART_FIFOSTS_RXOVIF_Pos (0)
11096#define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos)
11098#define UART_FIFOSTS_RXEMPTY_Pos (1)
11099#define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos)
11101#define UART_FIFOSTS_RXFULL_Pos (2)
11102#define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos)
11104#define UART_FIFOSTS_PEF_Pos (4)
11105#define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos)
11107#define UART_FIFOSTS_FEF_Pos (5)
11108#define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos)
11110#define UART_FIFOSTS_BIF_Pos (6)
11111#define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos)
11113#define UART_FIFOSTS_TXOVIF_Pos (8)
11114#define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos)
11116#define UART_FIFOSTS_TXEMPTY_Pos (9)
11117#define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos)
11119#define UART_FIFOSTS_TXFULL_Pos (10)
11120#define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos)
11122#define UART_FIFOSTS_TXENDF_Pos (11)
11123#define UART_FIFOSTS_TXENDF_Msk (0x1ul << UART_FIFOSTS_TXENDF_Pos)
11125#define UART_FIFOSTS_RXPTR_Pos (16)
11126#define UART_FIFOSTS_RXPTR_Msk (0x1ful << UART_FIFOSTS_RXPTR_Pos)
11128#define UART_FIFOSTS_TXPTR_Pos (24)
11129#define UART_FIFOSTS_TXPTR_Msk (0x1ful << UART_FIFOSTS_TXPTR_Pos)
11131#define UART_MODEM_RTSACTLV_Pos (0)
11132#define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos)
11134#define UART_MODEM_RTSSTS_Pos (1)
11135#define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos)
11137#define UART_MODEM_CTSACTLV_Pos (16)
11138#define UART_MODEM_CTSACTLV_Msk (0x1ul << UART_MODEM_CTSACTLV_Pos)
11140#define UART_MODEM_CTSSTS_Pos (17)
11141#define UART_MODEM_CTSSTS_Msk (0x1ul << UART_MODEM_CTSSTS_Pos)
11143#define UART_MODEM_CTSDETF_Pos (18)
11144#define UART_MODEM_CTSDETF_Msk (0x1ul << UART_MODEM_CTSDETF_Pos)
11146#define UART_TOUT_TOIC_Pos (0)
11147#define UART_TOUT_TOIC_Msk (0x1fful << UART_TOUT_TOIC_Pos)
11149#define UART_TOUT_DLY_Pos (16)
11150#define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos)
11152#define UART_BAUD_BRD_Pos (0)
11153#define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos)
11155#define UART_BAUD_DIV16EN_Pos (31)
11156#define UART_BAUD_DIV16EN_Msk (0x1ul << UART_BAUD_DIV16EN_Pos)
11158#define UART_IRDA_TXEN_Pos (1)
11159#define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos)
11161#define UART_IRDA_TXINV_Pos (5)
11162#define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos)
11164#define UART_IRDA_RXINV_Pos (6)
11165#define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos)
11167#define UART_ALTCTL_BRKFL_Pos (0)
11168#define UART_ALTCTL_BRKFL_Msk (0x7ul << UART_ALTCTL_BRKFL_Pos)
11170#define UART_ALTCTL_LINHSEL_Pos (4)
11171#define UART_ALTCTL_LINHSEL_Msk (0x3ul << UART_ALTCTL_LINHSEL_Pos)
11173#define UART_ALTCTL_LINRXEN_Pos (6)
11174#define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos)
11176#define UART_ALTCTL_LINTXEN_Pos (7)
11177#define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos)
11179#define UART_ALTCTL_BITERREN_Pos (8)
11180#define UART_ALTCTL_BITERREN_Msk (0x1ul << UART_ALTCTL_BITERREN_Pos)
11182#define UART_ALTCTL_RS485NMM_Pos (16)
11183#define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos)
11185#define UART_ALTCTL_RS485AAD_Pos (17)
11186#define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos)
11188#define UART_ALTCTL_RS485AUD_Pos (18)
11189#define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos)
11191#define UART_ALTCTL_ADDRDEN_Pos (19)
11192#define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos)
11194#define UART_ALTCTL_ADRMPID_Pos (24)
11195#define UART_ALTCTL_ADRMPID_Msk (0xfful << UART_ALTCTL_ADRMPID_Pos)
11197#define UART_FUNCSEL_FUNCSEL_Pos (0)
11198#define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos)
11200#define UART_BRCOMPAT_BRCOMPAT_Pos (0)
11201#define UART_BRCOMPAT_BRCOMPAT_Msk (0x1fful << UART_BRCOMPAT_BRCOMPAT_Pos)
11203#define UART_BRCOMPAT_BRCOMPDEC_Pos (31)
11204#define UART_BRCOMPAT_BRCOMPDEC_Msk (0x1ul << UART_BRCOMPAT_BRCOMPDEC_Pos)
11206#define UART_WKUPEN_WKCTSEN_Pos (0)
11207#define UART_WKUPEN_WKCTSEN_Msk (0x1ul << UART_WKUPEN_WKCTSEN_Pos)
11209#define UART_WKUPEN_WKDATEN_Pos (1)
11210#define UART_WKUPEN_WKDATEN_Msk (0x1ul << UART_WKUPEN_WKDATEN_Pos)
11212#define UART_WKUPEN_WKTHREN_Pos (2)
11213#define UART_WKUPEN_WKTHREN_Msk (0x1ul << UART_WKUPEN_WKTHREN_Pos)
11215#define UART_WKUPEN_WKTHRTOEN_Pos (3)
11216#define UART_WKUPEN_WKTHRTOEN_Msk (0x1ul << UART_WKUPEN_WKTHRTOEN_Pos)
11218#define UART_WKUPEN_WKADRMEN_Pos (4)
11219#define UART_WKUPEN_WKADRMEN_Msk (0x1ul << UART_WKUPEN_WKADRMEN_Pos)
11221#define UART_WKUPSTS_CTSWKSTS_Pos (0)
11222#define UART_WKUPSTS_CTSWKSTS_Msk (0x1ul << UART_WKUPSTS_CTSWKSTS_Pos)
11224#define UART_WKUPSTS_DATWKSTS_Pos (1)
11225#define UART_WKUPSTS_DATWKSTS_Msk (0x1ul << UART_WKUPSTS_DATWKSTS_Pos)
11227#define UART_WKUPSTS_THRWKSTS_Pos (2)
11228#define UART_WKUPSTS_THRWKSTS_Msk (0x1ul << UART_WKUPSTS_THRWKSTS_Pos)
11230#define UART_WKUPSTS_THRTOWKSTS_Pos (3)
11231#define UART_WKUPSTS_THRTOWKSTS_Msk (0x1ul << UART_WKUPSTS_THRTOWKSTS_Pos)
11233#define UART_WKUPSTS_ADRWKSTS_Pos (4)
11234#define UART_WKUPSTS_ADRWKSTS_Msk (0x1ul << UART_WKUPSTS_ADRWKSTS_Pos) /* UART_CONST */ /* end of UART register group */
11238
11239
11240/*---------------------- Smart Card Host Interface Controller -------------------------*/
11246typedef struct
11247{
11248
11249
11784 __IO uint32_t DAT;
11785 __IO uint32_t CTL;
11786 __IO uint32_t ALTCTL;
11787 __IO uint32_t EGT;
11788 __IO uint32_t RXTOUT;
11789 __IO uint32_t ETUCTL;
11790 __IO uint32_t INTEN;
11791 __IO uint32_t INTSTS;
11792 __IO uint32_t STATUS;
11793 __IO uint32_t PINCTL;
11794 __IO uint32_t TMRCTL0;
11795 __IO uint32_t TMRCTL1;
11796 __IO uint32_t TMRCTL2;
11797 __IO uint32_t UARTCTL;
11799 __I uint32_t RESERVE0[2];
11801 __IO uint32_t ACTCTL;
11803} SC_T;
11804
11810#define SC_DAT_DAT_Pos (0)
11811#define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos)
11813#define SC_CTL_SCEN_Pos (0)
11814#define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos)
11816#define SC_CTL_RXOFF_Pos (1)
11817#define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos)
11819#define SC_CTL_TXOFF_Pos (2)
11820#define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos)
11822#define SC_CTL_AUTOCEN_Pos (3)
11823#define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos)
11825#define SC_CTL_CONSEL_Pos (4)
11826#define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos)
11828#define SC_CTL_RXTRGLV_Pos (6)
11829#define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos)
11831#define SC_CTL_BGT_Pos (8)
11832#define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos)
11834#define SC_CTL_TMRSEL_Pos (13)
11835#define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos)
11837#define SC_CTL_NSB_Pos (15)
11838#define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos)
11840#define SC_CTL_RXRTY_Pos (16)
11841#define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos)
11843#define SC_CTL_RXRTYEN_Pos (19)
11844#define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos)
11846#define SC_CTL_TXRTY_Pos (20)
11847#define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos)
11849#define SC_CTL_TXRTYEN_Pos (23)
11850#define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos)
11852#define SC_CTL_CDDBSEL_Pos (24)
11853#define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos)
11855#define SC_CTL_SYNC_Pos (30)
11856#define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos)
11858#define SC_ALTCTL_TXRST_Pos (0)
11859#define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos)
11861#define SC_ALTCTL_RXRST_Pos (1)
11862#define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos)
11864#define SC_ALTCTL_DACTEN_Pos (2)
11865#define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos)
11867#define SC_ALTCTL_ACTEN_Pos (3)
11868#define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos)
11870#define SC_ALTCTL_WARSTEN_Pos (4)
11871#define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos)
11873#define SC_ALTCTL_CNTEN0_Pos (5)
11874#define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos)
11876#define SC_ALTCTL_CNTEN1_Pos (6)
11877#define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos)
11879#define SC_ALTCTL_CNTEN2_Pos (7)
11880#define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos)
11882#define SC_ALTCTL_INITSEL_Pos (8)
11883#define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos)
11885#define SC_ALTCTL_RXBGTEN_Pos (12)
11886#define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos)
11888#define SC_ALTCTL_ACTSTS0_Pos (13)
11889#define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos)
11891#define SC_ALTCTL_ACTSTS1_Pos (14)
11892#define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos)
11894#define SC_ALTCTL_ACTSTS2_Pos (15)
11895#define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos)
11897#define SC_ALTCTL_OUTSEL_Pos (16)
11898#define SC_ALTCTL_OUTSEL_Msk (0x1ul << SC_ALTCTL_OUTSEL_Pos)
11900#define SC_EGT_EGT_Pos (0)
11901#define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos)
11903#define SC_RXTOUT_RFTM_Pos (0)
11904#define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos)
11906#define SC_ETUCTL_ETURDIV_Pos (0)
11907#define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos)
11909#define SC_INTEN_RDAIEN_Pos (0)
11910#define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos)
11912#define SC_INTEN_TBEIEN_Pos (1)
11913#define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos)
11915#define SC_INTEN_TERRIEN_Pos (2)
11916#define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos)
11918#define SC_INTEN_TMR0IEN_Pos (3)
11919#define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos)
11921#define SC_INTEN_TMR1IEN_Pos (4)
11922#define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos)
11924#define SC_INTEN_TMR2IEN_Pos (5)
11925#define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos)
11927#define SC_INTEN_BGTIEN_Pos (6)
11928#define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos)
11930#define SC_INTEN_CDIEN_Pos (7)
11931#define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos)
11933#define SC_INTEN_INITIEN_Pos (8)
11934#define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos)
11936#define SC_INTEN_RXTOIEN_Pos (9)
11937#define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos)
11939#define SC_INTEN_ACERRIEN_Pos (10)
11940#define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos)
11942#define SC_INTSTS_RDAIF_Pos (0)
11943#define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos)
11945#define SC_INTSTS_TBEIF_Pos (1)
11946#define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos)
11948#define SC_INTSTS_TERRIF_Pos (2)
11949#define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos)
11951#define SC_INTSTS_TMR0IF_Pos (3)
11952#define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos)
11954#define SC_INTSTS_TMR1IF_Pos (4)
11955#define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos)
11957#define SC_INTSTS_TMR2IF_Pos (5)
11958#define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos)
11960#define SC_INTSTS_BGTIF_Pos (6)
11961#define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos)
11963#define SC_INTSTS_CDIF_Pos (7)
11964#define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos)
11966#define SC_INTSTS_INITIF_Pos (8)
11967#define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos)
11969#define SC_INTSTS_RXTOIF_Pos (9)
11970#define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos)
11972#define SC_INTSTS_ACERRIF_Pos (10)
11973#define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos)
11975#define SC_STATUS_RXOV_Pos (0)
11976#define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos)
11978#define SC_STATUS_RXEMPTY_Pos (1)
11979#define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos)
11981#define SC_STATUS_RXFULL_Pos (2)
11982#define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos)
11984#define SC_STATUS_PEF_Pos (4)
11985#define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos)
11987#define SC_STATUS_FEF_Pos (5)
11988#define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos)
11990#define SC_STATUS_BEF_Pos (6)
11991#define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos)
11993#define SC_STATUS_TXOV_Pos (8)
11994#define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos)
11996#define SC_STATUS_TXEMPTY_Pos (9)
11997#define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos)
11999#define SC_STATUS_TXFULL_Pos (10)
12000#define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos)
12002#define SC_STATUS_RXPOINT_Pos (16)
12003#define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos)
12005#define SC_STATUS_RXRERR_Pos (21)
12006#define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos)
12008#define SC_STATUS_RXOVERR_Pos (22)
12009#define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos)
12011#define SC_STATUS_RXACT_Pos (23)
12012#define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos)
12014#define SC_STATUS_TXPOINT_Pos (24)
12015#define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos)
12017#define SC_STATUS_TXRERR_Pos (29)
12018#define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos)
12020#define SC_STATUS_TXOVERR_Pos (30)
12021#define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos)
12023#define SC_STATUS_TXACT_Pos (31)
12024#define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos)
12026#define SC_PINCTL_PWREN_Pos (0)
12027#define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos)
12029#define SC_PINCTL_SCRST_Pos (1)
12030#define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos)
12032#define SC_PINCTL_CREMOVE_Pos (2)
12033#define SC_PINCTL_CREMOVE_Msk (0x1ul << SC_PINCTL_CREMOVE_Pos)
12035#define SC_PINCTL_CINSERT_Pos (3)
12036#define SC_PINCTL_CINSERT_Msk (0x1ul << SC_PINCTL_CINSERT_Pos)
12038#define SC_PINCTL_CDPINSTS_Pos (4)
12039#define SC_PINCTL_CDPINSTS_Msk (0x1ul << SC_PINCTL_CDPINSTS_Pos)
12041#define SC_PINCTL_CLKKEEP_Pos (6)
12042#define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos)
12044#define SC_PINCTL_ADACEN_Pos (7)
12045#define SC_PINCTL_ADACEN_Msk (0x1ul << SC_PINCTL_ADACEN_Pos)
12047#define SC_PINCTL_SCDOUT_Pos (9)
12048#define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos)
12050#define SC_PINCTL_CDLV_Pos (10)
12051#define SC_PINCTL_CDLV_Msk (0x1ul << SC_PINCTL_CDLV_Pos)
12053#define SC_PINCTL_PWRINV_Pos (11)
12054#define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos)
12056#define SC_PINCTL_DATSTS_Pos (16)
12057#define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos)
12059#define SC_PINCTL_SYNC_Pos (30)
12060#define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos)
12062#define SC_TMRCTL0_CNT_Pos (0)
12063#define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos)
12065#define SC_TMRCTL0_OPMODE_Pos (24)
12066#define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos)
12068#define SC_TMRCTL0_SYNC_Pos (31)
12069#define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos)
12071#define SC_TMRCTL1_CNT_Pos (0)
12072#define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos)
12074#define SC_TMRCTL1_OPMODE_Pos (24)
12075#define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos)
12077#define SC_TMRCTL1_SYNC_Pos (31)
12078#define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos)
12080#define SC_TMRCTL2_CNT_Pos (0)
12081#define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos)
12083#define SC_TMRCTL2_OPMODE_Pos (24)
12084#define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos)
12086#define SC_TMRCTL2_SYNC_Pos (31)
12087#define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos)
12089#define SC_UARTCTL_UARTEN_Pos (0)
12090#define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos)
12092#define SC_UARTCTL_WLS_Pos (4)
12093#define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos)
12095#define SC_UARTCTL_PBOFF_Pos (6)
12096#define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos)
12098#define SC_UARTCTL_OPE_Pos (7)
12099#define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos)
12101#define SC_ACTCTL_T1EXT_Pos (0)
12102#define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /* SC_CONST */ /* end of SC register group */
12106
12107
12108/*---------------------- Inter-IC Bus Controller -------------------------*/
12114typedef struct
12115{
12116
12117
12314 __IO uint32_t CTL;
12315 __IO uint32_t INTSTS;
12316 __I uint32_t STATUS;
12317 __IO uint32_t CLKDIV;
12318 __IO uint32_t TOCTL;
12319 __IO uint32_t DAT;
12320 __IO uint32_t ADDR0;
12321 __IO uint32_t ADDR1;
12323 __I uint32_t RESERVE0[2];
12325 __IO uint32_t ADDRMSK0;
12326 __IO uint32_t ADDRMSK1;
12328 __I uint32_t RESERVE1[4];
12330 __IO uint32_t CTL2;
12331 __IO uint32_t STATUS2;
12333} I2C_T;
12334
12340#define I2C_CTL_I2CEN_Pos (0)
12341#define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos)
12343#define I2C_CTL_AA_Pos (1)
12344#define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos)
12346#define I2C_CTL_STO_Pos (2)
12347#define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos)
12349#define I2C_CTL_STA_Pos (3)
12350#define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos)
12352#define I2C_CTL_SI_Pos (4)
12353#define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos)
12355#define I2C_CTL_INTEN_Pos (7)
12356#define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos)
12358#define I2C_INTSTS_INTSTS_Pos (0)
12359#define I2C_INTSTS_INTSTS_Msk (0x1ul << I2C_INTSTS_INTSTS_Pos)
12361#define I2C_INTSTS_TOIF_Pos (1)
12362#define I2C_INTSTS_TOIF_Msk (0x1ul << I2C_INTSTS_TOIF_Pos)
12364#define I2C_INTSTS_WKAKDONE_Pos (7)
12365#define I2C_INTSTS_WKAKDONE_Msk (0x1ul << I2C_INTSTS_WKAKDONE_Pos)
12367#define I2C_STATUS_STATUS_Pos (0)
12368#define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos)
12370#define I2C_CLKDIV_DIVIDER_Pos (0)
12371#define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos)
12373#define I2C_TOCTL_TOCEN_Pos (0)
12374#define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos)
12376#define I2C_TOCTL_TOCDIV4_Pos (1)
12377#define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos)
12379#define I2C_DAT_DAT_Pos (0)
12380#define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos)
12382#define I2C_ADDR0_GC_Pos (0)
12383#define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos)
12385#define I2C_ADDR0_ADDR_Pos (1)
12386#define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos)
12388#define I2C_ADDR1_GC_Pos (0)
12389#define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos)
12391#define I2C_ADDR1_ADDR_Pos (1)
12392#define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos)
12394#define I2C_ADDRMSK0_ADDRMSK_Pos (1)
12395#define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos)
12397#define I2C_ADDRMSK1_ADDRMSK_Pos (1)
12398#define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos)
12400#define I2C_CTL2_WKUPEN_Pos (0)
12401#define I2C_CTL2_WKUPEN_Msk (0x1ul << I2C_CTL2_WKUPEN_Pos)
12403#define I2C_CTL2_OVIEN_Pos (1)
12404#define I2C_CTL2_OVIEN_Msk (0x1ul << I2C_CTL2_OVIEN_Pos)
12406#define I2C_CTL2_URIEN_Pos (2)
12407#define I2C_CTL2_URIEN_Msk (0x1ul << I2C_CTL2_URIEN_Pos)
12409#define I2C_CTL2_TWOLVBUF_Pos (4)
12410#define I2C_CTL2_TWOLVBUF_Msk (0x1ul << I2C_CTL2_TWOLVBUF_Pos)
12412#define I2C_CTL2_NOSTRETCH_Pos (5)
12413#define I2C_CTL2_NOSTRETCH_Msk (0x1ul << I2C_CTL2_NOSTRETCH_Pos)
12415#define I2C_CTL2_DATMODE_Pos (6)
12416#define I2C_CTL2_DATMODE_Msk (0x1ul << I2C_CTL2_DATMODE_Pos)
12418#define I2C_CTL2_MSDAT_Pos (7)
12419#define I2C_CTL2_MSDAT_Msk (0x1ul << I2C_CTL2_MSDAT_Pos)
12421#define I2C_STATUS2_WKIF_Pos (0)
12422#define I2C_STATUS2_WKIF_Msk (0x1ul << I2C_STATUS2_WKIF_Pos)
12424#define I2C_STATUS2_OVIF_Pos (1)
12425#define I2C_STATUS2_OVIF_Msk (0x1ul << I2C_STATUS2_OVIF_Pos)
12427#define I2C_STATUS2_URIF_Pos (2)
12428#define I2C_STATUS2_URIF_Msk (0x1ul << I2C_STATUS2_URIF_Pos)
12430#define I2C_STATUS2_WRSTSWK_Pos (3)
12431#define I2C_STATUS2_WRSTSWK_Msk (0x1ul << I2C_STATUS2_WRSTSWK_Pos)
12433#define I2C_STATUS2_FULL_Pos (4)
12434#define I2C_STATUS2_FULL_Msk (0x1ul << I2C_STATUS2_FULL_Pos)
12436#define I2C_STATUS2_EMPTY_Pos (5)
12437#define I2C_STATUS2_EMPTY_Msk (0x1ul << I2C_STATUS2_EMPTY_Pos)
12439#define I2C_STATUS2_BUSFREE_Pos (6)
12440#define I2C_STATUS2_BUSFREE_Msk (0x1ul << I2C_STATUS2_BUSFREE_Pos) /* I2C_CONST */ /* end of I2C register group */
12444
12445
12446/*---------------------- Serial Peripheral Interface Controller -------------------------*/
12452typedef struct
12453{
12454
12455
12822 __IO uint32_t CTL;
12823 __IO uint32_t STATUS;
12824 __IO uint32_t CLKDIV;
12825 __IO uint32_t SSCTL;
12826 __I uint32_t RX0;
12827 __I uint32_t RX1;
12829 __I uint32_t RESERVE0[2];
12831 __O uint32_t TX0;
12832 __O uint32_t TX1;
12834 __I uint32_t RESERVE1[4];
12836 __IO uint32_t PDMACTL;
12837 __IO uint32_t FIFOCTL;
12838} SPI_T;
12839
12845#define SPI_CTL_GOBUSY_Pos (0)
12846#define SPI_CTL_GOBUSY_Msk (0x1ul << SPI_CTL_GOBUSY_Pos)
12848#define SPI_CTL_RXNEG_Pos (1)
12849#define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos)
12851#define SPI_CTL_TXNEG_Pos (2)
12852#define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos)
12854#define SPI_CTL_DWIDTH_Pos (3)
12855#define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos)
12857#define SPI_CTL_LSB_Pos (10)
12858#define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos)
12860#define SPI_CTL_CLKPOL_Pos (11)
12861#define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos)
12863#define SPI_CTL_SUSPITV_Pos (12)
12864#define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos)
12866#define SPI_CTL_UNITIEN_Pos (17)
12867#define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos)
12869#define SPI_CTL_SLAVE_Pos (18)
12870#define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos)
12872#define SPI_CTL_REORDER_Pos (19)
12873#define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos)
12875#define SPI_CTL_FIFOM_Pos (21)
12876#define SPI_CTL_FIFOM_Msk (0x1ul << SPI_CTL_FIFOM_Pos)
12878#define SPI_CTL_TWOBIT_Pos (22)
12879#define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos)
12881#define SPI_CTL_DUALDIR_Pos (28)
12882#define SPI_CTL_DUALDIR_Msk (0x1ul << SPI_CTL_DUALDIR_Pos)
12884#define SPI_CTL_DUALIOEN_Pos (29)
12885#define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos)
12887#define SPI_CTL_WKSSEN_Pos (30)
12888#define SPI_CTL_WKSSEN_Msk (0x1ul << SPI_CTL_WKSSEN_Pos)
12890#define SPI_CTL_WKCLKEN_Pos (31)
12891#define SPI_CTL_WKCLKEN_Msk (0x1ul << SPI_CTL_WKCLKEN_Pos)
12893#define SPI_STATUS_RXEMPTY_Pos (0)
12894#define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos)
12896#define SPI_STATUS_RXFULL_Pos (1)
12897#define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos)
12899#define SPI_STATUS_TXEMPTY_Pos (2)
12900#define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos)
12902#define SPI_STATUS_TXFULL_Pos (3)
12903#define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos)
12905#define SPI_STATUS_LTRIGF_Pos (4)
12906#define SPI_STATUS_LTRIGF_Msk (0x1ul << SPI_STATUS_LTRIGF_Pos)
12908#define SPI_STATUS_SLVSTAIF_Pos (6)
12909#define SPI_STATUS_SLVSTAIF_Msk (0x1ul << SPI_STATUS_SLVSTAIF_Pos)
12911#define SPI_STATUS_UNITIF_Pos (7)
12912#define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos)
12914#define SPI_STATUS_RXTHIF_Pos (8)
12915#define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos)
12917#define SPI_STATUS_RXOVIF_Pos (9)
12918#define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos)
12920#define SPI_STATUS_TXTHIF_Pos (10)
12921#define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos)
12923#define SPI_STATUS_RXTOIF_Pos (12)
12924#define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos)
12926#define SPI_STATUS_SLVTOIF_Pos (13)
12927#define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos)
12929#define SPI_STATUS_SLVTXSKE_Pos (15)
12930#define SPI_STATUS_SLVTXSKE_Msk (0x1ul << SPI_STATUS_SLVTXSKE_Pos)
12932#define SPI_STATUS_RXCNT_Pos (16)
12933#define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos)
12935#define SPI_STATUS_TXCNT_Pos (20)
12936#define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos)
12938#define SPI_STATUS_WKSSIF_Pos (30)
12939#define SPI_STATUS_WKSSIF_Msk (0x1ul << SPI_STATUS_WKSSIF_Pos)
12941#define SPI_STATUS_WKCLKIF_Pos (31)
12942#define SPI_STATUS_WKCLKIF_Msk (0x1ul << SPI_STATUS_WKCLKIF_Pos)
12944#define SPI_CLKDIV_DIVIDER_Pos (0)
12945#define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos)
12947#define SPI_SSCTL_SS_Pos (0)
12948#define SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos)
12950#define SPI_SSCTL_SSACTPOL_Pos (2)
12951#define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos)
12953#define SPI_SSCTL_AUTOSS_Pos (3)
12954#define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos)
12956#define SPI_SSCTL_SSLTRIG_Pos (4)
12957#define SPI_SSCTL_SSLTRIG_Msk (0x1ul << SPI_SSCTL_SSLTRIG_Pos)
12959#define SPI_SSCTL_SLV3WIRE_Pos (5)
12960#define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos)
12962#define SPI_SSCTL_SLVTOIEN_Pos (6)
12963#define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos)
12965#define SPI_SSCTL_SLVABORT_Pos (8)
12966#define SPI_SSCTL_SLVABORT_Msk (0x1ul << SPI_SSCTL_SLVABORT_Pos)
12968#define SPI_SSCTL_SSTAIEN_Pos (9)
12969#define SPI_SSCTL_SSTAIEN_Msk (0x1ul << SPI_SSCTL_SSTAIEN_Pos)
12971#define SPI_SSCTL_SSINAIEN_Pos (16)
12972#define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos)
12974#define SPI_SSCTL_SLVTOCNT_Pos (20)
12975#define SPI_SSCTL_SLVTOCNT_Msk (0x3fful << SPI_SSCTL_SLVTOCNT_Pos)
12977#define SPI_RX0_RX_Pos (0)
12978#define SPI_RX0_RX_Msk (0xfffffffful << SPI_RX0_RX_Pos)
12980#define SPI_RX1_RX_Pos (0)
12981#define SPI_RX1_RX_Msk (0xfffffffful << SPI_RX1_RX_Pos)
12983#define SPI_TX0_TX_Pos (0)
12984#define SPI_TX0_TX_Msk (0xfffffffful << SPI_TX0_TX_Pos)
12986#define SPI_TX1_TX_Pos (0)
12987#define SPI_TX1_TX_Msk (0xfffffffful << SPI_TX1_TX_Pos)
12989#define SPI_PDMACTL_TXPDMAEN_Pos (0)
12990#define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos)
12992#define SPI_PDMACTL_RXPDMAEN_Pos (1)
12993#define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos)
12995#define SPI_PDMACTL_PDMARST_Pos (2)
12996#define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos)
12998#define SPI_FIFOCTL_RXFBCLR_Pos (0)
12999#define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos)
13001#define SPI_FIFOCTL_TXFBCLR_Pos (1)
13002#define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos)
13004#define SPI_FIFOCTL_RXTHIEN_Pos (2)
13005#define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos)
13007#define SPI_FIFOCTL_TXTHIEN_Pos (3)
13008#define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos)
13010#define SPI_FIFOCTL_RXOVIEN_Pos (4)
13011#define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos)
13013#define SPI_FIFOCTL_RXTOIEN_Pos (7)
13014#define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos)
13016#define SPI_FIFOCTL_RXTH_Pos (24)
13017#define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos)
13019#define SPI_FIFOCTL_TXTH_Pos (28)
13020#define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /* SPI_CONST */ /* end of SPI register group */
13024
13025
13026/*---------------------- Analog to Digital Converter -------------------------*/
13032typedef struct
13033{
13034
13035
13375 __I uint32_t DAT[18];
13376 __IO uint32_t CTL;
13377 __IO uint32_t CHEN;
13378 __IO uint32_t CMP0;
13379 __IO uint32_t CMP1;
13380 __IO uint32_t STATUS;
13382 __I uint32_t RESERVE1[1];
13384 __I uint32_t PDMA;
13385 __IO uint32_t PWD;
13386 __IO uint32_t CALCTL;
13387 __IO uint32_t CALWORD;
13388 __IO uint32_t EXTSMPT0;
13389 __IO uint32_t EXTSMPT1;
13391} ADC_T;
13392
13398#define ADC_DAT0_RESULT_Pos (0)
13399#define ADC_DAT0_RESULT_Msk (0xffful << ADC_DAT0_RESULT_Pos)
13401#define ADC_DAT0_VALID_Pos (16)
13402#define ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos)
13404#define ADC_DAT0_OV_Pos (17)
13405#define ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos)
13407#define ADC_CTL_ADCEN_Pos (0)
13408#define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos)
13410#define ADC_CTL_ADCIEN_Pos (1)
13411#define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos)
13413#define ADC_CTL_ADMD_Pos (2)
13414#define ADC_CTL_ADMD_Msk (0x3ul << ADC_CTL_ADMD_Pos)
13416#define ADC_CTL_HWTRGSEL_Pos (4)
13417#define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos)
13419#define ADC_CTL_HWTRGCOND_Pos (6)
13420#define ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos)
13422#define ADC_CTL_HWTRGEN_Pos (8)
13423#define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos)
13425#define ADC_CTL_PTEN_Pos (9)
13426#define ADC_CTL_PTEN_Msk (0x1ul << ADC_CTL_PTEN_Pos)
13428#define ADC_CTL_DIFF_Pos (10)
13429#define ADC_CTL_DIFF_Msk (0x1ul << ADC_CTL_DIFF_Pos)
13431#define ADC_CTL_SWTRG_Pos (11)
13432#define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos)
13434#define ADC_CTL_TMSEL_Pos (12)
13435#define ADC_CTL_TMSEL_Msk (0x3ul << ADC_CTL_TMSEL_Pos)
13437#define ADC_CTL_TMTRGMOD_Pos (15)
13438#define ADC_CTL_TMTRGMOD_Msk (0x1ul << ADC_CTL_TMTRGMOD_Pos)
13440#define ADC_CTL_REFSEL_Pos (16)
13441#define ADC_CTL_REFSEL_Msk (0x3ul << ADC_CTL_REFSEL_Pos)
13443#define ADC_CTL_RESSEL_Pos (18)
13444#define ADC_CTL_RESSEL_Msk (0x3ul << ADC_CTL_RESSEL_Pos)
13446#define ADC_CTL_TMPDMACNT_Pos (24)
13447#define ADC_CTL_TMPDMACNT_Msk (0xfful << ADC_CTL_TMPDMACNT_Pos)
13449#define ADC_CHEN_CHEN0_Pos (0)
13450#define ADC_CHEN_CHEN0_Msk (0x1ul << ADC_CHEN_CHEN0_Pos)
13452#define ADC_CHEN_CHEN1_Pos (1)
13453#define ADC_CHEN_CHEN1_Msk (0x1ul << ADC_CHEN_CHEN1_Pos)
13455#define ADC_CHEN_CHEN2_Pos (2)
13456#define ADC_CHEN_CHEN2_Msk (0x1ul << ADC_CHEN_CHEN2_Pos)
13458#define ADC_CHEN_CHEN3_Pos (3)
13459#define ADC_CHEN_CHEN3_Msk (0x1ul << ADC_CHEN_CHEN3_Pos)
13461#define ADC_CHEN_CHEN4_Pos (4)
13462#define ADC_CHEN_CHEN4_Msk (0x1ul << ADC_CHEN_CHEN4_Pos)
13464#define ADC_CHEN_CHEN5_Pos (5)
13465#define ADC_CHEN_CHEN5_Msk (0x1ul << ADC_CHEN_CHEN5_Pos)
13467#define ADC_CHEN_CHEN6_Pos (6)
13468#define ADC_CHEN_CHEN6_Msk (0x1ul << ADC_CHEN_CHEN6_Pos)
13470#define ADC_CHEN_CHEN7_Pos (7)
13471#define ADC_CHEN_CHEN7_Msk (0x1ul << ADC_CHEN_CHEN7_Pos)
13473#define ADC_CHEN_CHEN12_Pos (12)
13474#define ADC_CHEN_CHEN12_Msk (0x1ul << ADC_CHEN_CHEN12_Pos)
13476#define ADC_CHEN_CHEN13_Pos (13)
13477#define ADC_CHEN_CHEN13_Msk (0x1ul << ADC_CHEN_CHEN13_Pos)
13479#define ADC_CHEN_CHEN14_Pos (14)
13480#define ADC_CHEN_CHEN14_Msk (0x1ul << ADC_CHEN_CHEN14_Pos)
13482#define ADC_CHEN_CHEN15_Pos (15)
13483#define ADC_CHEN_CHEN15_Msk (0x1ul << ADC_CHEN_CHEN15_Pos)
13485#define ADC_CHEN_CHEN16_Pos (16)
13486#define ADC_CHEN_CHEN16_Msk (0x1ul << ADC_CHEN_CHEN16_Pos)
13488#define ADC_CHEN_CHEN17_Pos (17)
13489#define ADC_CHEN_CHEN17_Msk (0x1ul << ADC_CHEN_CHEN17_Pos)
13491#define ADC_CMP0_ADCMPEN_Pos (0)
13492#define ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos)
13494#define ADC_CMP0_ADCMPIE_Pos (1)
13495#define ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos)
13497#define ADC_CMP0_CMPCOND_Pos (2)
13498#define ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos)
13500#define ADC_CMP0_CMPCH_Pos (3)
13501#define ADC_CMP0_CMPCH_Msk (0x1ful << ADC_CMP0_CMPCH_Pos)
13503#define ADC_CMP0_CMPMCNT_Pos (8)
13504#define ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos)
13506#define ADC_CMP0_CMPDAT_Pos (16)
13507#define ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos)
13509#define ADC_CMP1_ADCMPEN_Pos (0)
13510#define ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos)
13512#define ADC_CMP1_ADCMPIE_Pos (1)
13513#define ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos)
13515#define ADC_CMP1_CMPCOND_Pos (2)
13516#define ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos)
13518#define ADC_CMP1_CMPCH_Pos (3)
13519#define ADC_CMP1_CMPCH_Msk (0x1ful << ADC_CMP1_CMPCH_Pos)
13521#define ADC_CMP1_CMPMCNT_Pos (8)
13522#define ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos)
13524#define ADC_CMP1_CMPDAT_Pos (16)
13525#define ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos)
13527#define ADC_STATUS_ADIF_Pos (0)
13528#define ADC_STATUS_ADIF_Msk (0x1ul << ADC_STATUS_ADIF_Pos)
13530#define ADC_STATUS_ADCMPF0_Pos (1)
13531#define ADC_STATUS_ADCMPF0_Msk (0x1ul << ADC_STATUS_ADCMPF0_Pos)
13533#define ADC_STATUS_ADCMPF1_Pos (2)
13534#define ADC_STATUS_ADCMPF1_Msk (0x1ul << ADC_STATUS_ADCMPF1_Pos)
13536#define ADC_STATUS_BUSY_Pos (3)
13537#define ADC_STATUS_BUSY_Msk (0x1ul << ADC_STATUS_BUSY_Pos)
13539#define ADC_STATUS_CHANNEL_Pos (4)
13540#define ADC_STATUS_CHANNEL_Msk (0x1ful << ADC_STATUS_CHANNEL_Pos)
13542#define ADC_STATUS_INITRDY_Pos (16)
13543#define ADC_STATUS_INITRDY_Msk (0x1ul << ADC_STATUS_INITRDY_Pos)
13545#define ADC_PDMA_AD_PDMA_Pos (0)
13546#define ADC_PDMA_AD_PDMA_Msk (0xffful << ADC_PDMA_AD_PDMA_Pos)
13548#define ADC_PWD_PWUPRDY_Pos (0)
13549#define ADC_PWD_PWUPRDY_Msk (0x1ul << ADC_PWD_PWUPRDY_Pos)
13551#define ADC_PWD_PWDCALEN_Pos (1)
13552#define ADC_PWD_PWDCALEN_Msk (0x1ul << ADC_PWD_PWDCALEN_Pos)
13554#define ADC_PWD_PWDMOD_Pos (2)
13555#define ADC_PWD_PWDMOD_Msk (0x3ul << ADC_PWD_PWDMOD_Pos)
13557#define ADC_CALCTL_CALEN_Pos (0)
13558#define ADC_CALCTL_CALEN_Msk (0x1ul << ADC_CALCTL_CALEN_Pos)
13560#define ADC_CALCTL_CALSTART_Pos (1)
13561#define ADC_CALCTL_CALSTART_Msk (0x1ul << ADC_CALCTL_CALSTART_Pos)
13563#define ADC_CALCTL_CALDONE_Pos (2)
13564#define ADC_CALCTL_CALDONE_Msk (0x1ul << ADC_CALCTL_CALDONE_Pos)
13566#define ADC_CALCTL_CALSEL_Pos (3)
13567#define ADC_CALCTL_CALSEL_Msk (0x1ul << ADC_CALCTL_CALSEL_Pos)
13569#define ADC_CALWORD_CALWORD_Pos (0)
13570#define ADC_CALWORD_CALWORD_Msk (0x7ful << ADC_CALWORD_CALWORD_Pos)
13572#define ADC_EXTSMPT0_EXTSMPT_CH0_Pos (0)
13573#define ADC_EXTSMPT0_EXTSMPT_CH0_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH0_Pos)
13575#define ADC_EXTSMPT0_EXTSMPT_CH1_Pos (4)
13576#define ADC_EXTSMPT0_EXTSMPT_CH1_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH1_Pos)
13578#define ADC_EXTSMPT0_EXTSMPT_CH2_Pos (8)
13579#define ADC_EXTSMPT0_EXTSMPT_CH2_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH2_Pos)
13581#define ADC_EXTSMPT0_EXTSMPT_CH3_Pos (12)
13582#define ADC_EXTSMPT0_EXTSMPT_CH3_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH3_Pos)
13584#define ADC_EXTSMPT0_EXTSMPT_CH4_Pos (16)
13585#define ADC_EXTSMPT0_EXTSMPT_CH4_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH4_Pos)
13587#define ADC_EXTSMPT0_EXTSMPT_CH5_Pos (20)
13588#define ADC_EXTSMPT0_EXTSMPT_CH5_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH5_Pos)
13590#define ADC_EXTSMPT0_EXTSMPT_CH6_Pos (24)
13591#define ADC_EXTSMPT0_EXTSMPT_CH6_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH6_Pos)
13593#define ADC_EXTSMPT0_EXTSMPT_CH7_Pos (28)
13594#define ADC_EXTSMPT0_EXTSMPT_CH7_Msk (0xful << ADC_EXTSMPT0_EXTSMPT_CH7_Pos)
13596#define ADC_EXTSMPT1_EXTSMPT_INTCH_Pos (16)
13597#define ADC_EXTSMPT1_EXTSMPT_INTCH_Msk (0xful << ADC_EXTSMPT1_EXTSMPT_INTCH_Pos) /* ADC_CONST */ /* end of ADC register group */
13601
13602
13603/*---------------------- Analog Comparator Controller -------------------------*/
13609typedef struct
13610{
13611
13612
13665 __IO uint32_t CTL0;
13666 __IO uint32_t STATUS;
13667 __IO uint32_t VREF;
13669} ACMP_T;
13670
13676#define ACMP_CTL0_ACMPEN_Pos (0)
13677#define ACMP_CTL0_ACMPEN_Msk (0x1ul << ACMP_CTL0_ACMPEN_Pos)
13679#define ACMP_CTL0_ACMPIE_Pos (1)
13680#define ACMP_CTL0_ACMPIE_Msk (0x1ul << ACMP_CTL0_ACMPIE_Pos)
13682#define ACMP_CTL0_HYSEN_Pos (2)
13683#define ACMP_CTL0_HYSEN_Msk (0x1ul << ACMP_CTL0_HYSEN_Pos)
13685#define ACMP_CTL0_NEGSEL_Pos (4)
13686#define ACMP_CTL0_NEGSEL_Msk (0x3ul << ACMP_CTL0_NEGSEL_Pos)
13688#define ACMP_CTL0_WKEN_Pos (31)
13689#define ACMP_CTL0_WKEN_Msk (0x1ul << ACMP_CTL0_WKEN_Pos)
13691#define ACMP_STATUS_ACMPIF_Pos (0)
13692#define ACMP_STATUS_ACMPIF_Msk (0x1ul << ACMP_STATUS_ACMPIF_Pos)
13694#define ACMP_STATUS_ACMPO_Pos (1)
13695#define ACMP_STATUS_ACMPO_Msk (0x1ul << ACMP_STATUS_ACMPO_Pos)
13697#define ACMP_VREF_CRVCTL_Pos (0)
13698#define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos)
13700#define ACMP_VREF_CRVEN_Pos (4)
13701#define ACMP_VREF_CRVEN_Msk (0x1ul << ACMP_VREF_CRVEN_Pos)
13703#define ACMP_VREF_CRVSSEL_Pos (5)
13704#define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /* ACMP_CONST */ /* end of ACMP register group */
13708
13709
13710
13711#if defined ( __CC_ARM )
13712#pragma no_anon_unions
13713#endif
13714
13720#define FLASH_BASE ((uint32_t)0x00000000)
13721#define SRAM_BASE ((uint32_t)0x20000000)
13722#define APB1PERIPH_BASE ((uint32_t)0x40000000)
13723#define APB2PERIPH_BASE ((uint32_t)0x40100000)
13724#define AHBPERIPH_BASE ((uint32_t)0x50000000)
13725
13728#define WDT_BASE (APB1PERIPH_BASE + 0x04000)
13729#define WWDT_BASE (APB1PERIPH_BASE + 0x04100)
13730#define RTC_BASE (APB1PERIPH_BASE + 0x08000)
13731#define TIMER0_BASE (APB1PERIPH_BASE + 0x10000)
13732#define TIMER1_BASE (APB1PERIPH_BASE + 0x10100)
13733#define I2C0_BASE (APB1PERIPH_BASE + 0x20000)
13734#define SPI0_BASE (APB1PERIPH_BASE + 0x30000)
13735#define SPI2_BASE (APB1PERIPH_BASE + 0xD0000)
13736#define PWM0_BASE (APB1PERIPH_BASE + 0x40000)
13737#define UART0_BASE (APB1PERIPH_BASE + 0x50000)
13738#define LCD_BASE (APB1PERIPH_BASE + 0xB0000)
13739#define ADC_BASE (APB1PERIPH_BASE + 0xE0000)
13740
13741#define TIMER2_BASE (APB2PERIPH_BASE + 0x10000)
13742#define TIMER3_BASE (APB2PERIPH_BASE + 0x10100)
13743#define I2C1_BASE (APB2PERIPH_BASE + 0x20000)
13744#define SPI1_BASE (APB2PERIPH_BASE + 0x30000)
13745#define SPI3_BASE (APB2PERIPH_BASE + 0xE0000)
13746
13747#define UART1_BASE (APB2PERIPH_BASE + 0x50000)
13748#define SC0_BASE (APB2PERIPH_BASE + 0x90000)
13749#define SC1_BASE (APB2PERIPH_BASE + 0xB0000)
13750#define ACMP_BASE (APB2PERIPH_BASE + 0xD0000)
13751
13752#define SYS_BASE (AHBPERIPH_BASE + 0x00000)
13753#define CLK_BASE (AHBPERIPH_BASE + 0x00200)
13754#define INTID_BASE (AHBPERIPH_BASE + 0x00300)
13755#define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
13756#define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
13757#define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
13758#define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
13759#define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
13760#define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
13761#define GPIODBNCE_BASE (AHBPERIPH_BASE + 0x04180)
13762#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04200)
13763#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000)
13764#define PDMA1_BASE (AHBPERIPH_BASE + 0x08100)
13765#define PDMA2_BASE (AHBPERIPH_BASE + 0x08200)
13766#define PDMA3_BASE (AHBPERIPH_BASE + 0x08300)
13767#define PDMA4_BASE (AHBPERIPH_BASE + 0x08400)
13768#define PDMACRC_BASE (AHBPERIPH_BASE + 0x08E00)
13769#define PDMAGCR_BASE (AHBPERIPH_BASE + 0x08F00)
13770#define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
13771 /* end of group NANO103_PERIPHERAL_MEM_MAP */
13773
13774
13779#define WDT ((WDT_T *) WDT_BASE)
13780#define WWDT ((WWDT_T *) WWDT_BASE)
13781#define RTC ((RTC_T *) RTC_BASE)
13782#define TIMER0 ((TIMER_T *) TIMER0_BASE)
13783#define TIMER1 ((TIMER_T *) TIMER1_BASE)
13784#define TIMER2 ((TIMER_T *) TIMER2_BASE)
13785#define TIMER3 ((TIMER_T *) TIMER3_BASE)
13786#define I2C0 ((I2C_T *) I2C0_BASE)
13787#define I2C1 ((I2C_T *) I2C1_BASE)
13788#define SPI0 ((SPI_T *) SPI0_BASE)
13789#define SPI1 ((SPI_T *) SPI1_BASE)
13790#define SPI2 ((SPI_T *) SPI2_BASE)
13791#define SPI3 ((SPI_T *) SPI3_BASE)
13792#define PWM0 ((PWM_T *) PWM0_BASE)
13793#define UART0 ((UART_T *) UART0_BASE)
13794#define UART1 ((UART_T *) UART1_BASE)
13795#define LCD ((LCD_T *) LCD_BASE)
13796#define ADC ((ADC_T *) ADC_BASE)
13797#define SC0 ((SC_T *) SC0_BASE)
13798#define SC1 ((SC_T *) SC1_BASE)
13799#define ACMP ((ACMP_T *) ACMP_BASE)
13800
13801#define SYS ((SYS_T *) SYS_BASE)
13802#define CLK ((CLK_T *) CLK_BASE)
13803#define PA ((GPIO_T *) GPIOA_BASE)
13804#define PB ((GPIO_T *) GPIOB_BASE)
13805#define PC ((GPIO_T *) GPIOC_BASE)
13806#define PD ((GPIO_T *) GPIOD_BASE)
13807#define PE ((GPIO_T *) GPIOE_BASE)
13808#define PF ((GPIO_T *) GPIOF_BASE)
13809#define GPIO ((GP_DB_T *) GPIODBNCE_BASE)
13810#define PDMA1 ((PDMA_CH_T *) PDMA1_BASE)
13811#define PDMA2 ((PDMA_CH_T *) PDMA2_BASE)
13812#define PDMA3 ((PDMA_CH_T *) PDMA3_BASE)
13813#define PDMA4 ((PDMA_CH_T *) PDMA4_BASE)
13814#define PDMACRC ((DMA_CRC_T *) PDMACRC_BASE)
13815#define PDMAGCR ((DMA_GCR_T *) PDMAGCR_BASE)
13816#define FMC ((FMC_T *) FMC_BASE)
13817 /* end of group NANO103_PERIPHERAL_DECLARATION */
13819 /* end of group NANO103_Peripherals */
13821
13827typedef volatile unsigned char vu8;
13828typedef volatile unsigned short vu16;
13829typedef volatile unsigned long vu32;
13830
13836#define M8(addr) (*((vu8 *) (addr)))
13837
13844#define M16(addr) (*((vu16 *) (addr)))
13845
13852#define M32(addr) (*((vu32 *) (addr)))
13853
13861#define outpw(port,value) *((volatile unsigned int *)(port)) = value
13862
13869#define inpw(port) (*((volatile unsigned int *)(port)))
13870
13878#define outps(port,value) *((volatile unsigned short *)(port)) = value
13879
13886#define inps(port) (*((volatile unsigned short *)(port)))
13887
13894#define outpb(port,value) *((volatile unsigned char *)(port)) = value
13895
13901#define inpb(port) (*((volatile unsigned char *)(port)))
13902
13910#define outp32(port,value) *((volatile unsigned int *)(port)) = value
13911
13918#define inp32(port) (*((volatile unsigned int *)(port)))
13919
13927#define outp16(port,value) *((volatile unsigned short *)(port)) = value
13928
13935#define inp16(port) (*((volatile unsigned short *)(port)))
13936
13943#define outp8(port,value) *((volatile unsigned char *)(port)) = value
13944
13950#define inp8(port) (*((volatile unsigned char *)(port)))
13951 /* end of group NANO103_IO_ROUTINE */
13953
13954/******************************************************************************/
13955/* Legacy Constants */
13956/******************************************************************************/
13962#ifndef NULL
13963#define NULL (0)
13964#endif
13965
13966#define TRUE (1)
13967#define FALSE (0)
13968
13969#define ENABLE (1)
13970#define DISABLE (0)
13971
13972/* Define one bit mask */
13973#define BIT0 (0x00000001)
13974#define BIT1 (0x00000002)
13975#define BIT2 (0x00000004)
13976#define BIT3 (0x00000008)
13977#define BIT4 (0x00000010)
13978#define BIT5 (0x00000020)
13979#define BIT6 (0x00000040)
13980#define BIT7 (0x00000080)
13981#define BIT8 (0x00000100)
13982#define BIT9 (0x00000200)
13983#define BIT10 (0x00000400)
13984#define BIT11 (0x00000800)
13985#define BIT12 (0x00001000)
13986#define BIT13 (0x00002000)
13987#define BIT14 (0x00004000)
13988#define BIT15 (0x00008000)
13989#define BIT16 (0x00010000)
13990#define BIT17 (0x00020000)
13991#define BIT18 (0x00040000)
13992#define BIT19 (0x00080000)
13993#define BIT20 (0x00100000)
13994#define BIT21 (0x00200000)
13995#define BIT22 (0x00400000)
13996#define BIT23 (0x00800000)
13997#define BIT24 (0x01000000)
13998#define BIT25 (0x02000000)
13999#define BIT26 (0x04000000)
14000#define BIT27 (0x08000000)
14001#define BIT28 (0x10000000)
14002#define BIT29 (0x20000000)
14003#define BIT30 (0x40000000)
14004#define BIT31 (0x80000000)
14005
14006/* Byte Mask Definitions */
14007#define BYTE0_Msk (0x000000FF)
14008#define BYTE1_Msk (0x0000FF00)
14009#define BYTE2_Msk (0x00FF0000)
14010#define BYTE3_Msk (0xFF000000)
14011
14012#define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) )
14013#define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8)
14014#define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16)
14015#define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /* end of group NANO103_legacy_Constants */
14018 /* end of group NANO103_Definitions */
14020
14021#ifdef __cplusplus
14022}
14023#endif
14024
14025
14026/******************************************************************************/
14027/* Peripheral header files */
14028/******************************************************************************/
14029#include "sys.h"
14030#include "clk.h"
14031#include "acmp.h"
14032#include "adc.h"
14033#include "fmc.h"
14034#include "gpio.h"
14035#include "i2c.h"
14036#include "crc.h"
14037#include "pdma.h"
14038#include "pwm.h"
14039#include "rtc.h"
14040#include "sc.h"
14041#include "scuart.h"
14042#include "spi.h"
14043#include "timer.h"
14044#include "uart.h"
14045#include "wdt.h"
14046#include "wwdt.h"
14047
14048#endif // __NANO103_H__
14049
14050/*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/
14051
NANO103 series Analog Comparator(ACMP) driver header file.
NANO103 series ADC driver header file.
NANO103 series CLK driver header file.
NANO103 series CRC driver header file.
NANO103 Series Flash Memory Controller Driver Header File.
NANO103 series GPIO driver header file.
enum IRQn IRQn_Type
IRQn
Definition: Nano103.h:81
@ PendSV_IRQn
Definition: Nano103.h:87
@ EINT0_IRQn
Definition: Nano103.h:93
@ GPABC_IRQn
Definition: Nano103.h:95
@ I2C0_IRQn
Definition: Nano103.h:108
@ SC0_IRQn
Definition: Nano103.h:110
@ SVCall_IRQn
Definition: Nano103.h:86
@ ADC_IRQn
Definition: Nano103.h:116
@ SPI3_IRQn
Definition: Nano103.h:114
@ PDWU_IRQn
Definition: Nano103.h:115
@ SPI2_IRQn
Definition: Nano103.h:106
@ CKSD_IRQn
Definition: Nano103.h:112
@ SysTick_IRQn
Definition: Nano103.h:88
@ ACMP_IRQn
Definition: Nano103.h:117
@ WDT_IRQn
Definition: Nano103.h:92
@ PDMA_IRQn
Definition: Nano103.h:113
@ TMR1_IRQn
Definition: Nano103.h:99
@ TMR2_IRQn
Definition: Nano103.h:100
@ UART1_IRQn
Definition: Nano103.h:103
@ SPI1_IRQn
Definition: Nano103.h:105
@ HardFault_IRQn
Definition: Nano103.h:85
@ GPDEF_IRQn
Definition: Nano103.h:96
@ TMR0_IRQn
Definition: Nano103.h:98
@ HIRC_IRQn
Definition: Nano103.h:107
@ BOD_IRQn
Definition: Nano103.h:91
@ EINT1_IRQn
Definition: Nano103.h:94
@ RTC_IRQn
Definition: Nano103.h:118
@ NonMaskableInt_IRQn
Definition: Nano103.h:84
@ TMR3_IRQn
Definition: Nano103.h:101
@ SC1_IRQn
Definition: Nano103.h:111
@ PWM0_IRQn
Definition: Nano103.h:97
@ UART0_IRQn
Definition: Nano103.h:102
@ I2C1_IRQn
Definition: Nano103.h:109
@ SPI0_IRQn
Definition: Nano103.h:104
volatile unsigned long vu32
Define 32-bit unsigned volatile data type.
Definition: Nano103.h:13829
volatile unsigned short vu16
Define 16-bit unsigned volatile data type.
Definition: Nano103.h:13828
volatile unsigned char vu8
Define 8-bit unsigned volatile data type.
Definition: Nano103.h:13827
__IO uint32_t CTL0
Definition: Nano103.h:13665
__IO uint32_t DAT
Definition: Nano103.h:10927
__IO uint32_t CNT
Definition: Nano103.h:7751
__IO uint32_t TRSR
Definition: Nano103.h:10932
__I uint32_t FCAPDAT2
Definition: Nano103.h:8999
__IO uint32_t PWRCTL
Definition: Nano103.h:2626
__I uint32_t CCNTn
Definition: Nano103.h:7009
__IO uint32_t DTCTL2_3
Definition: Nano103.h:8954
__O uint32_t KEY1
Definition: Nano103.h:3248
__IO uint32_t FTCTL
Definition: Nano103.h:3239
__IO uint32_t DAT
Definition: Nano103.h:11784
__I uint32_t IRQ30_SRC
Definition: Nano103.h:440
__IO uint32_t ISPCMD
Definition: Nano103.h:3236
__IO uint32_t CLKFMT
Definition: Nano103.h:10128
__I uint32_t IRQ12_SRC
Definition: Nano103.h:422
__IO uint32_t EXTSMPT1
Definition: Nano103.h:13389
__IO uint32_t INTEN
Definition: Nano103.h:10930
__I uint32_t RX0
Definition: Nano103.h:12826
__IO uint32_t CNTEN
Definition: Nano103.h:8940
__I uint32_t IRQ29_SRC
Definition: Nano103.h:439
__IO uint32_t TMRCTL2
Definition: Nano103.h:11796
__I uint32_t PBUF4
Definition: Nano103.h:9023
__IO uint32_t FIFOSTS
Definition: Nano103.h:10933
__I uint32_t RCAPDAT5
Definition: Nano103.h:9004
__IO uint32_t IRC1TCTL
Definition: Nano103.h:1601
__IO uint32_t IPRST2
Definition: Nano103.h:1551
__IO uint32_t ISPTRG
Definition: Nano103.h:3237
__I uint32_t IRQ11_SRC
Definition: Nano103.h:421
__O uint32_t REGLCTL
Definition: Nano103.h:1613
__IO uint32_t ALTCTL
Definition: Nano103.h:11786
__IO uint32_t GPA_MFPH
Definition: Nano103.h:1568
__IO uint32_t SELFTEST
Definition: Nano103.h:9014
__IO uint32_t IRC1TIEN
Definition: Nano103.h:1602
__IO uint32_t ALTCTL
Definition: Nano103.h:10941
__I uint32_t CHECKSUM
Definition: Nano103.h:7188
__IO uint32_t CLKSRC
Definition: Nano103.h:8936
__IO uint32_t REQSEL1
Definition: Nano103.h:7292
__IO uint32_t CLKOCTL
Definition: Nano103.h:2636
__IO uint32_t LXTCTL
Definition: Nano103.h:10143
__I uint32_t IRQ6_SRC
Definition: Nano103.h:416
__IO uint32_t INTSTS
Definition: Nano103.h:7750
__IO uint32_t SAn
Definition: Nano103.h:7001
__O uint32_t TX1
Definition: Nano103.h:12832
__IO uint32_t INTEN
Definition: Nano103.h:9650
__IO uint32_t ETUCTL
Definition: Nano103.h:11789
__I uint32_t CMPBUF1
Definition: Nano103.h:9028
__IO uint32_t CALWORD
Definition: Nano103.h:13387
__IO uint32_t PUEN
Definition: Nano103.h:6148
__IO uint32_t CLKDIV1
Definition: Nano103.h:2634
__I uint32_t FCAPDAT3
Definition: Nano103.h:9001
__IO uint32_t TAMPCTL
Definition: Nano103.h:10146
__IO uint32_t DBCTL
Definition: Nano103.h:6187
__I uint32_t IRQ8_SRC
Definition: Nano103.h:418
__IO uint32_t MIRCTCTL
Definition: Nano103.h:1607
__IO uint32_t LXTICTL
Definition: Nano103.h:10145
__I uint32_t WKSTS
Definition: Nano103.h:1594
__IO uint32_t RSTSTS
Definition: Nano103.h:1549
__I uint32_t IRQ5_SRC
Definition: Nano103.h:415
__IO uint32_t CLKSEL1
Definition: Nano103.h:2631
__I uint32_t RCAPDAT2
Definition: Nano103.h:8998
__I uint32_t CSAn
Definition: Nano103.h:7007
__IO uint32_t RWEN
Definition: Nano103.h:10124
__IO uint32_t FREQADJ
Definition: Nano103.h:10125
__IO uint32_t WGCTL0
Definition: Nano103.h:8963
__I uint32_t RCAPDAT3
Definition: Nano103.h:9000
__IO uint32_t DINOFF
Definition: Nano103.h:6140
__IO uint32_t IVREFCTL
Definition: Nano103.h:1588
__IO uint32_t ADDRMSK1
Definition: Nano103.h:12326
__IO uint32_t CNTCLR
Definition: Nano103.h:8941
__IO uint32_t INTEN1
Definition: Nano103.h:8976
__IO uint32_t INTSTS0
Definition: Nano103.h:8977
__IO uint32_t MIRCTISTS
Definition: Nano103.h:1609
__IO uint32_t CAMSK
Definition: Nano103.h:10137
__I uint32_t IRQ24_SRC
Definition: Nano103.h:434
__IO uint32_t FIFOCTL
Definition: Nano103.h:12837
__IO uint32_t PWD
Definition: Nano103.h:13385
__IO uint32_t GPB_MFPH
Definition: Nano103.h:1570
__IO uint32_t IRC1TISTS
Definition: Nano103.h:1603
__IO uint32_t CLKPSC0_1
Definition: Nano103.h:8937
__IO uint32_t STATUS
Definition: Nano103.h:12823
__IO uint32_t ADCTS0
Definition: Nano103.h:8982
__IO uint32_t DBEN
Definition: Nano103.h:6144
__IO uint32_t CTL
Definition: Nano103.h:12822
__IO uint32_t KEYSTS
Definition: Nano103.h:3251
__IO uint32_t CMP1
Definition: Nano103.h:13379
__IO uint32_t CNTn
Definition: Nano103.h:7003
__IO uint32_t ADDR0
Definition: Nano103.h:12320
__IO uint32_t INTEN
Definition: Nano103.h:11790
__IO uint32_t DTCTL0_1
Definition: Nano103.h:8953
__IO uint32_t INTSTS
Definition: Nano103.h:10134
__IO uint32_t TOCTL
Definition: Nano103.h:12318
__IO uint32_t ACTCTL
Definition: Nano103.h:11801
__IO uint32_t CLKDIV0
Definition: Nano103.h:2633
__I uint32_t IRQ19_SRC
Definition: Nano103.h:429
__IO uint32_t CLKSEL0
Definition: Nano103.h:2630
__IO uint32_t BATDIVCTL
Definition: Nano103.h:1590
__IO uint32_t MODE
Definition: Nano103.h:6139
__I uint32_t CMPBUF3
Definition: Nano103.h:9030
__IO uint32_t PORCTL
Definition: Nano103.h:1583
__IO uint32_t DMABCNT
Definition: Nano103.h:7172
__I uint32_t FCAPDAT1
Definition: Nano103.h:8997
__IO uint32_t CLKDIV
Definition: Nano103.h:12317
__IO uint32_t DATMSK
Definition: Nano103.h:6142
__IO uint32_t MIRCTIEN
Definition: Nano103.h:1608
__I uint32_t IRQ18_SRC
Definition: Nano103.h:428
__IO uint32_t CTL
Definition: Nano103.h:11785
__IO uint32_t LXTOCTL
Definition: Nano103.h:10144
__IO uint32_t MSKEN
Definition: Nano103.h:8965
__I uint32_t IRQ10_SRC
Definition: Nano103.h:420
__IO uint32_t FUNCSEL
Definition: Nano103.h:10942
__IO uint32_t BAUD
Definition: Nano103.h:10936
__IO uint32_t CMP0
Definition: Nano103.h:13378
__I uint32_t CMPBUF2
Definition: Nano103.h:9029
__I uint32_t FCAPDAT5
Definition: Nano103.h:9005
__IO uint32_t CTL
Definition: Nano103.h:12314
__IO uint32_t CAPIF
Definition: Nano103.h:9010
__I uint32_t CAPSTS
Definition: Nano103.h:8993
__IO uint32_t VREF
Definition: Nano103.h:13667
__I uint32_t RX1
Definition: Nano103.h:12827
__I uint32_t IRQ7_SRC
Definition: Nano103.h:417
__I uint32_t FCAPDAT0
Definition: Nano103.h:8995
__IO uint32_t DMASA
Definition: Nano103.h:7168
__IO uint32_t DAT
Definition: Nano103.h:12319
__I uint32_t IRQ28_SRC
Definition: Nano103.h:438
__I uint32_t IRQ20_SRC
Definition: Nano103.h:430
__IO uint32_t ISPSTS
Definition: Nano103.h:3243
__IO uint32_t INTSTS1
Definition: Nano103.h:8978
__IO uint32_t REQSEL0
Definition: Nano103.h:7291
__IO uint32_t PDMACTL
Definition: Nano103.h:12836
__I uint32_t STATUS
Definition: Nano103.h:2629
__I uint32_t PIN
Definition: Nano103.h:6143
__I uint32_t RCAPDAT4
Definition: Nano103.h:9002
__IO uint32_t ADDR1
Definition: Nano103.h:12321
__IO uint32_t POLCTL
Definition: Nano103.h:8972
__IO uint32_t RPDBCLK
Definition: Nano103.h:1617
__IO uint32_t RCCFCTL
Definition: Nano103.h:1563
__IO uint32_t TAMSK
Definition: Nano103.h:10136
__IO uint32_t ISPADDR
Definition: Nano103.h:3234
__IO uint32_t STATUS
Definition: Nano103.h:11792
__IO uint32_t GPE_MFPL
Definition: Nano103.h:1575
__IO uint32_t DMAINTEN
Definition: Nano103.h:7181
__IO uint32_t GCTL
Definition: Nano103.h:7290
__I uint32_t IRQ3_SRC
Definition: Nano103.h:413
__IO uint32_t WKUPEN
Definition: Nano103.h:10944
__I uint32_t IRQ9_SRC
Definition: Nano103.h:419
__IO uint32_t PINCTL
Definition: Nano103.h:11793
__IO uint32_t INTTYPE
Definition: Nano103.h:6145
__IO uint32_t STATUS2
Definition: Nano103.h:12331
__IO uint32_t CMP
Definition: Nano103.h:7748
__IO uint32_t TMRCTL0
Definition: Nano103.h:11794
__IO uint32_t INTEN0
Definition: Nano103.h:8975
__O uint32_t SWBRK
Definition: Nano103.h:8974
__I uint32_t CMPBUF0
Definition: Nano103.h:9027
__I uint32_t CAP
Definition: Nano103.h:7752
__I uint32_t CNT
Definition: Nano103.h:9766
__IO uint32_t CTL0
Definition: Nano103.h:8931
__IO uint32_t KEYTRG
Definition: Nano103.h:3250
__IO uint32_t INTSTSn
Definition: Nano103.h:7011
__IO uint32_t CTL
Definition: Nano103.h:7746
__IO uint32_t CTL
Definition: Nano103.h:7167
__IO uint32_t CTLn
Definition: Nano103.h:7000
__IO uint32_t WGCTL1
Definition: Nano103.h:8964
__IO uint32_t NMI_SEL
Definition: Nano103.h:442
__IO uint32_t MISCCTL
Definition: Nano103.h:1555
__IO uint32_t LDOCTL
Definition: Nano103.h:1589
__I uint32_t IRQ21_SRC
Definition: Nano103.h:431
__I uint32_t IRQ14_SRC
Definition: Nano103.h:424
__IO uint32_t SSCTL
Definition: Nano103.h:12825
__IO uint32_t CHEN
Definition: Nano103.h:13377
__I uint32_t IRQ26_SRC
Definition: Nano103.h:436
__IO uint32_t AHBCLK
Definition: Nano103.h:2627
__IO uint32_t CLKPSC2_3
Definition: Nano103.h:8938
__IO uint32_t TMRCTL1
Definition: Nano103.h:11795
__IO uint32_t DOUT
Definition: Nano103.h:6141
__IO uint32_t GPD_MFPL
Definition: Nano103.h:1573
__I uint32_t KPCNT
Definition: Nano103.h:3253
__IO uint32_t INTEN
Definition: Nano103.h:9764
__I uint32_t DMACSA
Definition: Nano103.h:7176
__IO uint32_t TOCn
Definition: Nano103.h:7012
__IO uint32_t MISCCTL
Definition: Nano103.h:10150
__IO uint32_t STATUS
Definition: Nano103.h:9765
__I uint32_t PDID
Definition: Nano103.h:1548
__I uint32_t DMACBCNT
Definition: Nano103.h:7180
__IO uint32_t GPA_MFPL
Definition: Nano103.h:1567
__IO uint32_t INTEN
Definition: Nano103.h:6146
__IO uint32_t INIT
Definition: Nano103.h:10123
__IO uint32_t SEED
Definition: Nano103.h:7187
__IO uint32_t CLKPSC4_5
Definition: Nano103.h:8939
__IO uint32_t ISPDAT
Definition: Nano103.h:3235
__I uint32_t IRQ16_SRC
Definition: Nano103.h:426
__I uint32_t DFBA
Definition: Nano103.h:3238
__IO uint32_t CDUPB
Definition: Nano103.h:2645
__I uint32_t IRQ15_SRC
Definition: Nano103.h:425
__IO uint32_t BODCTL
Definition: Nano103.h:1584
__IO uint32_t MODEM
Definition: Nano103.h:10934
__I uint32_t CMPBUF5
Definition: Nano103.h:9032
__IO uint32_t APBCLK
Definition: Nano103.h:2628
__IO uint32_t IRC0TCTL
Definition: Nano103.h:1595
__IO uint32_t EXTSMPT0
Definition: Nano103.h:13388
__I uint32_t CDAn
Definition: Nano103.h:7008
__I uint32_t LEAPYEAR
Definition: Nano103.h:10132
__IO uint32_t APBDIV
Definition: Nano103.h:2641
__IO uint32_t IRC0TIEN
Definition: Nano103.h:1596
__IO uint32_t CALCTL
Definition: Nano103.h:13386
__IO uint32_t ADDRMSK0
Definition: Nano103.h:12325
__IO uint32_t CAPINEN
Definition: Nano103.h:8991
__IO uint32_t CLKDCTL
Definition: Nano103.h:2642
__IO uint32_t DMAISTS
Definition: Nano103.h:7182
__I uint32_t GINTSTS
Definition: Nano103.h:7293
__IO uint32_t CLKDIV
Definition: Nano103.h:12824
__IO uint32_t DTCTL4_5
Definition: Nano103.h:8955
__IO uint32_t CTL
Definition: Nano103.h:13376
__IO uint32_t SPRCTL
Definition: Nano103.h:10138
__IO uint32_t INTSTS
Definition: Nano103.h:11791
__IO uint32_t TALM
Definition: Nano103.h:10130
__IO uint32_t UARTCTL
Definition: Nano103.h:11797
__IO uint32_t CALM
Definition: Nano103.h:10131
__I uint32_t IRQ2_SRC
Definition: Nano103.h:412
__IO uint32_t CLKDSTS
Definition: Nano103.h:2644
__IO uint32_t BNF
Definition: Nano103.h:8967
__I uint32_t RCAPDAT1
Definition: Nano103.h:8996
__IO uint32_t BRKCTL2_3
Definition: Nano103.h:8970
__O uint32_t RLDCNT
Definition: Nano103.h:9762
__IO uint32_t ECTL
Definition: Nano103.h:7756
__IO uint32_t INTEN
Definition: Nano103.h:10133
__IO uint32_t INTENn
Definition: Nano103.h:7010
__I uint32_t PBUF0
Definition: Nano103.h:9015
__I uint32_t IRQ22_SRC
Definition: Nano103.h:432
__IO uint32_t GPC_MFPH
Definition: Nano103.h:1572
__IO uint32_t IRC0TISTS
Definition: Nano103.h:1597
__IO uint32_t TOUT
Definition: Nano103.h:10935
__IO uint32_t IRDA
Definition: Nano103.h:10940
__IO uint32_t TIME
Definition: Nano103.h:10126
__I uint32_t IRQ27_SRC
Definition: Nano103.h:437
__I uint32_t IRQ23_SRC
Definition: Nano103.h:433
__I uint32_t INTSTS
Definition: Nano103.h:6149
__IO uint32_t CTRL
Definition: Nano103.h:10928
__IO uint32_t CLKSEL2
Definition: Nano103.h:2632
__IO uint32_t PRECNT
Definition: Nano103.h:7747
__I uint32_t IRQ0_SRC
Definition: Nano103.h:410
__IO uint32_t CTL
Definition: Nano103.h:9763
__IO uint32_t MSK
Definition: Nano103.h:8966
__IO uint32_t CTL1
Definition: Nano103.h:8932
__IO uint32_t STATUS
Definition: Nano103.h:9651
__IO uint32_t WKUPSTS
Definition: Nano103.h:10945
__IO uint32_t CAL
Definition: Nano103.h:10127
__IO uint32_t GPC_MFPL
Definition: Nano103.h:1571
__IO uint32_t INTSRC
Definition: Nano103.h:6147
__I uint32_t IRQ17_SRC
Definition: Nano103.h:427
__IO uint32_t WKINTSTS
Definition: Nano103.h:2640
__I uint32_t IRQ13_SRC
Definition: Nano103.h:423
__IO uint32_t STATUS
Definition: Nano103.h:13380
__IO uint32_t TICK
Definition: Nano103.h:10135
__IO uint32_t RXTOUT
Definition: Nano103.h:11788
__IO uint32_t CDLOWB
Definition: Nano103.h:2646
__IO uint32_t CTL2
Definition: Nano103.h:12330
__I uint32_t IRQ31_SRC
Definition: Nano103.h:441
__I uint32_t IRQ25_SRC
Definition: Nano103.h:435
__IO uint32_t DAT
Definition: Nano103.h:7186
__IO uint32_t INTSTS
Definition: Nano103.h:10931
__IO uint32_t TEMPCTL
Definition: Nano103.h:1559
__IO uint32_t WEEKDAY
Definition: Nano103.h:10129
__IO uint32_t CAPIEN
Definition: Nano103.h:9009
__IO uint32_t GPD_MFPH
Definition: Nano103.h:1574
__IO uint32_t INTEN
Definition: Nano103.h:7749
__I uint32_t IRQ4_SRC
Definition: Nano103.h:414
__IO uint32_t POEN
Definition: Nano103.h:8973
__IO uint32_t CTL
Definition: Nano103.h:9649
__IO uint32_t BRCOMPAT
Definition: Nano103.h:10943
__IO uint32_t STATUS
Definition: Nano103.h:13666
__IO uint32_t MCU_IRQ
Definition: Nano103.h:443
__IO uint32_t ADCTS1
Definition: Nano103.h:8983
__IO uint32_t CLKDIE
Definition: Nano103.h:2643
__I uint32_t STATUS
Definition: Nano103.h:12316
__I uint32_t PBUF2
Definition: Nano103.h:9019
__IO uint32_t EGT
Definition: Nano103.h:11787
__IO uint32_t STATUS
Definition: Nano103.h:8987
__I uint32_t FCAPDAT4
Definition: Nano103.h:9003
__O uint32_t KEY2
Definition: Nano103.h:3249
__I uint32_t CMPBUF4
Definition: Nano103.h:9031
__IO uint32_t CAPCTL
Definition: Nano103.h:8992
__IO uint32_t ISPCTL
Definition: Nano103.h:3233
__I uint32_t PDMA
Definition: Nano103.h:13384
__I uint32_t KECNT
Definition: Nano103.h:3252
__IO uint32_t FAILBRK
Definition: Nano103.h:8968
__IO uint32_t BRKCTL0_1
Definition: Nano103.h:8969
__IO uint32_t GPF_MFPL
Definition: Nano103.h:1579
__O uint32_t TX0
Definition: Nano103.h:12831
__IO uint32_t DAn
Definition: Nano103.h:7002
__IO uint32_t PLLCTL
Definition: Nano103.h:2635
__I uint32_t IRQ1_SRC
Definition: Nano103.h:411
__IO uint32_t GPB_MFPL
Definition: Nano103.h:1569
__IO uint32_t BRKCTL4_5
Definition: Nano103.h:8971
__O uint32_t KEY0
Definition: Nano103.h:3247
__IO uint32_t IPRST1
Definition: Nano103.h:1550
__IO uint32_t LINE
Definition: Nano103.h:10929
__IO uint32_t INTSTS
Definition: Nano103.h:12315
__I uint32_t RCAPDAT0
Definition: Nano103.h:8994
NANO103 series I2C driver header file.
NANO103 series PDMA driver header file.
NANO103 series PWM driver header file.
NANO103 series RTC driver header file.
NANO103 series Smartcard (SC) driver header file.
NANO103 series SPI driver header file.
Definition: Nano103.h:162
Definition: Nano103.h:566
NANO103 Series system control header file.
Nano103 system clock definition file.
NANO103 series TIMER driver header file.
NANO103 Series UART control header file.
NANO103 series WDT driver header file.
NANO103 series WWDT driver header file.