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enum | IRQn {
NonMaskableInt_IRQn = -14
,
HardFault_IRQn = -13
,
SVCall_IRQn = -5
,
PendSV_IRQn = -2
,
SysTick_IRQn = -1
,
BOD_IRQn = 0
,
WDT_IRQn = 1
,
EINT0_IRQn = 2
,
EINT1_IRQn = 3
,
GPABC_IRQn = 4
,
GPDEF_IRQn = 5
,
PWM0_IRQn = 6
,
TMR0_IRQn = 8
,
TMR1_IRQn = 9
,
TMR2_IRQn = 10
,
TMR3_IRQn = 11
,
UART0_IRQn = 12
,
UART1_IRQn = 13
,
SPI0_IRQn = 14
,
SPI1_IRQn = 15
,
SPI2_IRQn = 16
,
HIRC_IRQn = 17
,
I2C0_IRQn = 18
,
I2C1_IRQn = 19
,
SC0_IRQn = 21
,
SC1_IRQn = 22
,
CKSD_IRQn = 24
,
PDMA_IRQn = 26
,
SPI3_IRQn = 27
,
PDWU_IRQn = 28
,
ADC_IRQn = 29
,
ACMP_IRQn = 30
,
RTC_IRQn = 31
} |
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#define | SYS_PDID_PDID_Pos (0) |
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#define | SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) |
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#define | SYS_RSTSTS_PORF_Pos (0) |
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#define | SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) |
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#define | SYS_RSTSTS_PINRF_Pos (1) |
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#define | SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) |
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#define | SYS_RSTSTS_WDTRF_Pos (2) |
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#define | SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) |
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#define | SYS_RSTSTS_LVRF_Pos (3) |
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#define | SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) |
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#define | SYS_RSTSTS_BODRF_Pos (4) |
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#define | SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) |
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#define | SYS_RSTSTS_SYSRF_Pos (5) |
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#define | SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) |
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#define | SYS_RSTSTS_CPURF_Pos (7) |
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#define | SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) |
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#define | SYS_RSTSTS_LOCKRF_Pos (8) |
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#define | SYS_RSTSTS_LOCKRF_Msk (0x1ul << SYS_RSTSTS_LOCKRF_Pos) |
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#define | SYS_IPRST1_CHIPRST_Pos (0) |
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#define | SYS_IPRST1_CHIPRST_Msk (0x1ul << SYS_IPRST1_CHIPRST_Pos) |
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#define | SYS_IPRST1_CPURST_Pos (1) |
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#define | SYS_IPRST1_CPURST_Msk (0x1ul << SYS_IPRST1_CPURST_Pos) |
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#define | SYS_IPRST1_PDMARST_Pos (2) |
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#define | SYS_IPRST1_PDMARST_Msk (0x1ul << SYS_IPRST1_PDMARST_Pos) |
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#define | SYS_IPRST2_GPIORST_Pos (1) |
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#define | SYS_IPRST2_GPIORST_Msk (0x1ul << SYS_IPRST2_GPIORST_Pos) |
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#define | SYS_IPRST2_TMR0RST_Pos (2) |
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#define | SYS_IPRST2_TMR0RST_Msk (0x1ul << SYS_IPRST2_TMR0RST_Pos) |
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#define | SYS_IPRST2_TMR1RST_Pos (3) |
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#define | SYS_IPRST2_TMR1RST_Msk (0x1ul << SYS_IPRST2_TMR1RST_Pos) |
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#define | SYS_IPRST2_TMR2RST_Pos (4) |
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#define | SYS_IPRST2_TMR2RST_Msk (0x1ul << SYS_IPRST2_TMR2RST_Pos) |
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#define | SYS_IPRST2_TMR3RST_Pos (5) |
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#define | SYS_IPRST2_TMR3RST_Msk (0x1ul << SYS_IPRST2_TMR3RST_Pos) |
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#define | SYS_IPRST2_I2C0RST_Pos (8) |
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#define | SYS_IPRST2_I2C0RST_Msk (0x1ul << SYS_IPRST2_I2C0RST_Pos) |
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#define | SYS_IPRST2_I2C1RST_Pos (9) |
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#define | SYS_IPRST2_I2C1RST_Msk (0x1ul << SYS_IPRST2_I2C1RST_Pos) |
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#define | SYS_IPRST2_SPI0RST_Pos (12) |
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#define | SYS_IPRST2_SPI0RST_Msk (0x1ul << SYS_IPRST2_SPI0RST_Pos) |
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#define | SYS_IPRST2_SPI1RST_Pos (13) |
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#define | SYS_IPRST2_SPI1RST_Msk (0x1ul << SYS_IPRST2_SPI1RST_Pos) |
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#define | SYS_IPRST2_SPI2RST_Pos (14) |
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#define | SYS_IPRST2_SPI2RST_Msk (0x1ul << SYS_IPRST2_SPI2RST_Pos) |
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#define | SYS_IPRST2_SPI3RST_Pos (15) |
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#define | SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) |
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#define | SYS_IPRST2_UART0RST_Pos (16) |
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#define | SYS_IPRST2_UART0RST_Msk (0x1ul << SYS_IPRST2_UART0RST_Pos) |
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#define | SYS_IPRST2_UART1RST_Pos (17) |
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#define | SYS_IPRST2_UART1RST_Msk (0x1ul << SYS_IPRST2_UART1RST_Pos) |
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#define | SYS_IPRST2_PWM0RST_Pos (20) |
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#define | SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) |
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#define | SYS_IPRST2_ACMP0RST_Pos (22) |
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#define | SYS_IPRST2_ACMP0RST_Msk (0x1ul << SYS_IPRST2_ACMP0RST_Pos) |
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#define | SYS_IPRST2_ADCRST_Pos (28) |
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#define | SYS_IPRST2_ADCRST_Msk (0x1ul << SYS_IPRST2_ADCRST_Pos) |
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#define | SYS_IPRST2_SC0RST_Pos (30) |
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#define | SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) |
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#define | SYS_IPRST2_SC1RST_Pos (31) |
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#define | SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) |
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#define | SYS_MISCCTL_POR33DIS_Pos (6) |
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#define | SYS_MISCCTL_POR33DIS_Msk (0x1ul << SYS_MISCCTL_POR33DIS_Pos) |
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#define | SYS_MISCCTL_POR18DIS_Pos (7) |
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#define | SYS_MISCCTL_POR18DIS_Msk (0x1ul << SYS_MISCCTL_POR18DIS_Pos) |
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#define | SYS_TEMPCTL_VTEMPEN_Pos (0) |
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#define | SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos) |
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#define | SYS_RCCFCTL_HIRC0FEN_Pos (0) |
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#define | SYS_RCCFCTL_HIRC0FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC0FEN_Pos) |
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#define | SYS_RCCFCTL_HIRC1FEN_Pos (1) |
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#define | SYS_RCCFCTL_HIRC1FEN_Msk (0x1ul << SYS_RCCFCTL_HIRC1FEN_Pos) |
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#define | SYS_RCCFCTL_MRCFEN_Pos (2) |
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#define | SYS_RCCFCTL_MRCFEN_Msk (0x1ul << SYS_RCCFCTL_MRCFEN_Pos) |
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#define | SYS_GPA_MFPL_PA0MFP_Pos (0) |
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#define | SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) |
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#define | SYS_GPA_MFPL_PA1MFP_Pos (4) |
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#define | SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) |
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#define | SYS_GPA_MFPL_PA2MFP_Pos (8) |
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#define | SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) |
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#define | SYS_GPA_MFPL_PA3MFP_Pos (12) |
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#define | SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) |
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#define | SYS_GPA_MFPL_PA4MFP_Pos (16) |
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#define | SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) |
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#define | SYS_GPA_MFPL_PA5MFP_Pos (20) |
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#define | SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) |
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#define | SYS_GPA_MFPL_PA6MFP_Pos (24) |
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#define | SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) |
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#define | SYS_GPA_MFPH_PA8MFP_Pos (0) |
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#define | SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) |
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#define | SYS_GPA_MFPH_PA9MFP_Pos (4) |
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#define | SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) |
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#define | SYS_GPA_MFPH_PA10MFP_Pos (8) |
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#define | SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) |
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#define | SYS_GPA_MFPH_PA11MFP_Pos (12) |
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#define | SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) |
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#define | SYS_GPA_MFPH_PA12MFP_Pos (16) |
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#define | SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) |
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#define | SYS_GPA_MFPH_PA13MFP_Pos (20) |
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#define | SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) |
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#define | SYS_GPA_MFPH_PA14MFP_Pos (24) |
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#define | SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) |
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#define | SYS_GPA_MFPH_PA15MFP_Pos (28) |
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#define | SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) |
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#define | SYS_GPB_MFPL_PB0MFP_Pos (0) |
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#define | SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) |
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#define | SYS_GPB_MFPL_PB1MFP_Pos (4) |
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#define | SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) |
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#define | SYS_GPB_MFPL_PB2MFP_Pos (8) |
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#define | SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) |
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#define | SYS_GPB_MFPL_PB3MFP_Pos (12) |
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#define | SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) |
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#define | SYS_GPB_MFPL_PB4MFP_Pos (16) |
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#define | SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) |
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#define | SYS_GPB_MFPL_PB5MFP_Pos (20) |
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#define | SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) |
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#define | SYS_GPB_MFPL_PB6MFP_Pos (24) |
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#define | SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) |
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#define | SYS_GPB_MFPL_PB7MFP_Pos (28) |
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#define | SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) |
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#define | SYS_GPB_MFPH_PB8MFP_Pos (0) |
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#define | SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) |
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#define | SYS_GPB_MFPH_PB9MFP_Pos (4) |
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#define | SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) |
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#define | SYS_GPB_MFPH_PB10MFP_Pos (8) |
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#define | SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) |
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#define | SYS_GPB_MFPH_PB11MFP_Pos (12) |
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#define | SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) |
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#define | SYS_GPB_MFPH_PB13MFP_Pos (20) |
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#define | SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) |
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#define | SYS_GPB_MFPH_PB14MFP_Pos (24) |
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#define | SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) |
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#define | SYS_GPB_MFPH_PB15MFP_Pos (28) |
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#define | SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) |
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#define | SYS_GPC_MFPL_PC0MFP_Pos (0) |
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#define | SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) |
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#define | SYS_GPC_MFPL_PC1MFP_Pos (4) |
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#define | SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) |
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#define | SYS_GPC_MFPL_PC2MFP_Pos (8) |
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#define | SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) |
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#define | SYS_GPC_MFPL_PC3MFP_Pos (12) |
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#define | SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) |
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#define | SYS_GPC_MFPL_PC6MFP_Pos (24) |
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#define | SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) |
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#define | SYS_GPC_MFPL_PC7MFP_Pos (28) |
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#define | SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) |
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#define | SYS_GPC_MFPH_PC8MFP_Pos (0) |
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#define | SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) |
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#define | SYS_GPC_MFPH_PC9MFP_Pos (4) |
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#define | SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) |
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#define | SYS_GPC_MFPH_PC10MFP_Pos (8) |
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#define | SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) |
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#define | SYS_GPC_MFPH_PC11MFP_Pos (12) |
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#define | SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) |
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#define | SYS_GPC_MFPH_PC14MFP_Pos (24) |
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#define | SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) |
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#define | SYS_GPC_MFPH_PC15MFP_Pos (28) |
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#define | SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) |
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#define | SYS_GPD_MFPL_PD6MFP_Pos (24) |
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#define | SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) |
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#define | SYS_GPD_MFPL_PD7MFP_Pos (28) |
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#define | SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) |
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#define | SYS_GPD_MFPH_PD14MFP_Pos (24) |
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#define | SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) |
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#define | SYS_GPD_MFPH_PD15MFP_Pos (28) |
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#define | SYS_GPD_MFPH_PD15MFP_Msk (0x7ul << SYS_GPD_MFPH_PD15MFP_Pos) |
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#define | SYS_GPE_MFPL_PE5MFP_Pos (20) |
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#define | SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) |
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#define | SYS_GPF_MFPL_PF0MFP_Pos (0) |
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#define | SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) |
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#define | SYS_GPF_MFPL_PF1MFP_Pos (4) |
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#define | SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) |
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#define | SYS_GPF_MFPL_PF2MFP_Pos (8) |
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#define | SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) |
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#define | SYS_GPF_MFPL_PF3MFP_Pos (12) |
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#define | SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) |
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#define | SYS_GPF_MFPL_PF6MFP_Pos (24) |
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#define | SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) |
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#define | SYS_GPF_MFPL_PF7MFP_Pos (28) |
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#define | SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) |
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#define | SYS_PORCTL_POROFF_Pos (0) |
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#define | SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) |
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#define | SYS_BODCTL_BODEN_Pos (0) |
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#define | SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) |
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#define | SYS_BODCTL_BODIE_Pos (2) |
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#define | SYS_BODCTL_BODIE_Msk (0x1ul << SYS_BODCTL_BODIE_Pos) |
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#define | SYS_BODCTL_BODREN_Pos (3) |
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#define | SYS_BODCTL_BODREN_Msk (0x1ul << SYS_BODCTL_BODREN_Pos) |
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#define | SYS_BODCTL_BODIF_Pos (4) |
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#define | SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) |
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#define | SYS_BODCTL_BODOUT_Pos (6) |
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#define | SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) |
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#define | SYS_BODCTL_LVREN_Pos (7) |
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#define | SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) |
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#define | SYS_BODCTL_LPBODEN_Pos (8) |
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#define | SYS_BODCTL_LPBODEN_Msk (0x1ul << SYS_BODCTL_LPBODEN_Pos) |
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#define | SYS_BODCTL_LPBODVL_Pos (9) |
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#define | SYS_BODCTL_LPBODVL_Msk (0x1ul << SYS_BODCTL_LPBODVL_Pos) |
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#define | SYS_BODCTL_LPBODIE_Pos (10) |
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#define | SYS_BODCTL_LPBODIE_Msk (0x1ul << SYS_BODCTL_LPBODIE_Pos) |
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#define | SYS_BODCTL_LPBODREN_Pos (11) |
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#define | SYS_BODCTL_LPBODREN_Msk (0x1ul << SYS_BODCTL_LPBODREN_Pos) |
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#define | SYS_BODCTL_BODVL_Pos (12) |
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#define | SYS_BODCTL_BODVL_Msk (0xful << SYS_BODCTL_BODVL_Pos) |
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#define | SYS_BODCTL_LPBOD20TRIM_Pos (16) |
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#define | SYS_BODCTL_LPBOD20TRIM_Msk (0xful << SYS_BODCTL_LPBOD20TRIM_Pos) |
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#define | SYS_BODCTL_LPBOD25TRIM_Pos (20) |
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#define | SYS_BODCTL_LPBOD25TRIM_Msk (0xful << SYS_BODCTL_LPBOD25TRIM_Pos) |
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#define | SYS_BODCTL_BODDGSEL_Pos (24) |
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#define | SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) |
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#define | SYS_BODCTL_LVRDGSEL_Pos (28) |
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#define | SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) |
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#define | SYS_IVREFCTL_BGPEN_Pos (0) |
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#define | SYS_IVREFCTL_BGPEN_Msk (0x1ul << SYS_IVREFCTL_BGPEN_Pos) |
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#define | SYS_IVREFCTL_REGEN_Pos (1) |
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#define | SYS_IVREFCTL_REGEN_Msk (0x1ul << SYS_IVREFCTL_REGEN_Pos) |
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#define | SYS_IVREFCTL_SEL25_Pos (2) |
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#define | SYS_IVREFCTL_SEL25_Msk (0x3ul << SYS_IVREFCTL_SEL25_Pos) |
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#define | SYS_IVREFCTL_EXTMODE_Pos (4) |
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#define | SYS_IVREFCTL_EXTMODE_Msk (0x1ul << SYS_IVREFCTL_EXTMODE_Pos) |
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#define | SYS_IVREFCTL_VREFTRIM_Pos (8) |
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#define | SYS_IVREFCTL_VREFTRIM_Msk (0xful << SYS_IVREFCTL_VREFTRIM_Pos) |
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#define | SYS_LDOCTL_FASTWK_Pos (1) |
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#define | SYS_LDOCTL_FASTWK_Msk (0x1ul << SYS_LDOCTL_FASTWK_Pos) |
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#define | SYS_LDOCTL_LDOLVL_Pos (2) |
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#define | SYS_LDOCTL_LDOLVL_Msk (0x3ul << SYS_LDOCTL_LDOLVL_Pos) |
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#define | SYS_LDOCTL_LPRMEN_Pos (4) |
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#define | SYS_LDOCTL_LPRMEN_Msk (0x1ul << SYS_LDOCTL_LPRMEN_Pos) |
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#define | SYS_LDOCTL_FMCLVEN_Pos (5) |
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#define | SYS_LDOCTL_FMCLVEN_Msk (0x1ul << SYS_LDOCTL_FMCLVEN_Pos) |
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#define | SYS_BATDIVCTL_BATDIV2EN_Pos (0) |
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#define | SYS_BATDIVCTL_BATDIV2EN_Msk (0x1ul << SYS_BATDIVCTL_BATDIV2EN_Pos) |
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#define | SYS_WKSTS_ACMPWK_Pos (0) |
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#define | SYS_WKSTS_ACMPWK_Msk (0x1ul << SYS_WKSTS_ACMPWK_Pos) |
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#define | SYS_WKSTS_I2C1WK_Pos (1) |
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#define | SYS_WKSTS_I2C1WK_Msk (0x1ul << SYS_WKSTS_I2C1WK_Pos) |
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#define | SYS_WKSTS_I2C0WK_Pos (2) |
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#define | SYS_WKSTS_I2C0WK_Msk (0x1ul << SYS_WKSTS_I2C0WK_Pos) |
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#define | SYS_WKSTS_TMR3WK_Pos (3) |
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#define | SYS_WKSTS_TMR3WK_Msk (0x1ul << SYS_WKSTS_TMR3WK_Pos) |
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#define | SYS_WKSTS_TMR2WK_Pos (4) |
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#define | SYS_WKSTS_TMR2WK_Msk (0x1ul << SYS_WKSTS_TMR2WK_Pos) |
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#define | SYS_WKSTS_TMR1WK_Pos (5) |
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#define | SYS_WKSTS_TMR1WK_Msk (0x1ul << SYS_WKSTS_TMR1WK_Pos) |
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#define | SYS_WKSTS_TMR0WK_Pos (6) |
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#define | SYS_WKSTS_TMR0WK_Msk (0x1ul << SYS_WKSTS_TMR0WK_Pos) |
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#define | SYS_WKSTS_WDTWK_Pos (7) |
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#define | SYS_WKSTS_WDTWK_Msk (0x1ul << SYS_WKSTS_WDTWK_Pos) |
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#define | SYS_WKSTS_BODWK_Pos (8) |
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#define | SYS_WKSTS_BODWK_Msk (0x1ul << SYS_WKSTS_BODWK_Pos) |
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#define | SYS_WKSTS_SPI3WK_Pos (9) |
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#define | SYS_WKSTS_SPI3WK_Msk (0x1ul << SYS_WKSTS_SPI3WK_Pos) |
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#define | SYS_WKSTS_SPI2WK_Pos (10) |
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#define | SYS_WKSTS_SPI2WK_Msk (0x1ul << SYS_WKSTS_SPI2WK_Pos) |
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#define | SYS_WKSTS_SPI1WK_Pos (11) |
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#define | SYS_WKSTS_SPI1WK_Msk (0x1ul << SYS_WKSTS_SPI1WK_Pos) |
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#define | SYS_WKSTS_SPI0WK_Pos (12) |
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#define | SYS_WKSTS_SPI0WK_Msk (0x1ul << SYS_WKSTS_SPI0WK_Pos) |
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#define | SYS_WKSTS_UART1WK_Pos (13) |
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#define | SYS_WKSTS_UART1WK_Msk (0x1ul << SYS_WKSTS_UART1WK_Pos) |
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#define | SYS_WKSTS_UART0WK_Pos (14) |
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#define | SYS_WKSTS_UART0WK_Msk (0x1ul << SYS_WKSTS_UART0WK_Pos) |
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#define | SYS_WKSTS_RTCWK_Pos (15) |
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#define | SYS_WKSTS_RTCWK_Msk (0x1ul << SYS_WKSTS_RTCWK_Pos) |
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#define | SYS_WKSTS_GPIOWK_Pos (16) |
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#define | SYS_WKSTS_GPIOWK_Msk (0x1ul << SYS_WKSTS_GPIOWK_Pos) |
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#define | SYS_IRC0TCTL_FREQSEL_Pos (0) |
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#define | SYS_IRC0TCTL_FREQSEL_Msk (0x7ul << SYS_IRC0TCTL_FREQSEL_Pos) |
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#define | SYS_IRC0TCTL_LOOPSEL_Pos (4) |
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#define | SYS_IRC0TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC0TCTL_LOOPSEL_Pos) |
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#define | SYS_IRC0TCTL_RETRYCNT_Pos (6) |
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#define | SYS_IRC0TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC0TCTL_RETRYCNT_Pos) |
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#define | SYS_IRC0TCTL_CESTOPEN_Pos (8) |
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#define | SYS_IRC0TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC0TCTL_CESTOPEN_Pos) |
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#define | SYS_IRC0TIEN_TFAILIEN_Pos (1) |
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#define | SYS_IRC0TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC0TIEN_TFAILIEN_Pos) |
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#define | SYS_IRC0TIEN_CLKEIEN_Pos (2) |
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#define | SYS_IRC0TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC0TIEN_CLKEIEN_Pos) |
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#define | SYS_IRC0TISTS_FREQLOCK_Pos (0) |
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#define | SYS_IRC0TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC0TISTS_FREQLOCK_Pos) |
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#define | SYS_IRC0TISTS_TFAILIF_Pos (1) |
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#define | SYS_IRC0TISTS_TFAILIF_Msk (0x1ul << SYS_IRC0TISTS_TFAILIF_Pos) |
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#define | SYS_IRC0TISTS_CLKERRIF_Pos (2) |
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#define | SYS_IRC0TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC0TISTS_CLKERRIF_Pos) |
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#define | SYS_IRC1TCTL_FREQSEL_Pos (0) |
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#define | SYS_IRC1TCTL_FREQSEL_Msk (0x3ul << SYS_IRC1TCTL_FREQSEL_Pos) |
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#define | SYS_IRC1TCTL_LOOPSEL_Pos (4) |
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#define | SYS_IRC1TCTL_LOOPSEL_Msk (0x3ul << SYS_IRC1TCTL_LOOPSEL_Pos) |
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#define | SYS_IRC1TCTL_RETRYCNT_Pos (6) |
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#define | SYS_IRC1TCTL_RETRYCNT_Msk (0x3ul << SYS_IRC1TCTL_RETRYCNT_Pos) |
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#define | SYS_IRC1TCTL_CESTOPEN_Pos (8) |
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#define | SYS_IRC1TCTL_CESTOPEN_Msk (0x1ul << SYS_IRC1TCTL_CESTOPEN_Pos) |
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#define | SYS_IRC1TIEN_TFAILIEN_Pos (1) |
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#define | SYS_IRC1TIEN_TFAILIEN_Msk (0x1ul << SYS_IRC1TIEN_TFAILIEN_Pos) |
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#define | SYS_IRC1TIEN_CLKEIEN_Pos (2) |
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#define | SYS_IRC1TIEN_CLKEIEN_Msk (0x1ul << SYS_IRC1TIEN_CLKEIEN_Pos) |
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#define | SYS_IRC1TISTS_FREQLOCK_Pos (0) |
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#define | SYS_IRC1TISTS_FREQLOCK_Msk (0x1ul << SYS_IRC1TISTS_FREQLOCK_Pos) |
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#define | SYS_IRC1TISTS_TFAILIF_Pos (1) |
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#define | SYS_IRC1TISTS_TFAILIF_Msk (0x1ul << SYS_IRC1TISTS_TFAILIF_Pos) |
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#define | SYS_IRC1TISTS_CLKERRIF_Pos (2) |
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#define | SYS_IRC1TISTS_CLKERRIF_Msk (0x1ul << SYS_IRC1TISTS_CLKERRIF_Pos) |
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#define | SYS_MIRCTCTL_FREQSEL_Pos (0) |
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#define | SYS_MIRCTCTL_FREQSEL_Msk (0x3ul << SYS_MIRCTCTL_FREQSEL_Pos) |
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#define | SYS_MIRCTCTL_LOOPSEL_Pos (4) |
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#define | SYS_MIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_MIRCTCTL_LOOPSEL_Pos) |
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#define | SYS_MIRCTCTL_RETRYCNT_Pos (6) |
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#define | SYS_MIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_MIRCTCTL_RETRYCNT_Pos) |
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#define | SYS_MIRCTCTL_CESTOPEN_Pos (8) |
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#define | SYS_MIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_MIRCTCTL_CESTOPEN_Pos) |
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#define | SYS_MIRCTIEN_TFAILIEN_Pos (1) |
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#define | SYS_MIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_MIRCTIEN_TFAILIEN_Pos) |
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#define | SYS_MIRCTIEN_CLKEIEN_Pos (2) |
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#define | SYS_MIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_MIRCTIEN_CLKEIEN_Pos) |
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#define | SYS_MIRCTISTS_FREQLOCK_Pos (0) |
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#define | SYS_MIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_MIRCTISTS_FREQLOCK_Pos) |
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#define | SYS_MIRCTISTS_TFAILIF_Pos (1) |
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#define | SYS_MIRCTISTS_TFAILIF_Msk (0x1ul << SYS_MIRCTISTS_TFAILIF_Pos) |
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#define | SYS_MIRCTISTS_CLKERRIF_Pos (2) |
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#define | SYS_MIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_MIRCTISTS_CLKERRIF_Pos) |
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#define | SYS_REGLCTL_REGLCTL_Pos (0) |
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#define | SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) |
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#define | SYS_RPDBCLK_RSTPDBCLK_Pos (6) |
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#define | SYS_RPDBCLK_RSTPDBCLK_Msk (0x1ul << SYS_RPDBCLK_RSTPDBCLK_Pos) |
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