NANO103 BSP V3.01.004
The Board Support Package for Nano103 Series
clk.c
Go to the documentation of this file.
1/**************************************************************************/
13#include "Nano103.h"
22int32_t g_CLK_i32ErrCode = 0;
34{
35 /* Disable CKO clock source */
36 CLK->APBCLK &= (~CLK_APBCLK_CLKOCKEN_Msk);
37}
38
58void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
59{
60 /* Select CKO clock source */
61 CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_CLKOSEL_Msk)) | u32ClkSrc;
62
63 /* CKO = clock source / 2^(u32ClkDiv + 1) */
64 CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En<<CLK_CLKOCTL_DIV1EN_Pos);
65
66 /* Enable CKO clock source */
68}
69
70
76void CLK_PowerDown(void)
77{
78
79 SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
81 __WFI();
82
83}
84
90void CLK_Idle(void)
91{
92 CLK->PWRCTL &= ~(CLK_PWRCTL_PDEN_Msk);
93 __WFI();
94}
95
101uint32_t CLK_GetHXTFreq(void)
102{
103 if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN )
104 return __HXT;
105 else
106 return 0;
107}
108
114uint32_t CLK_GetLXTFreq(void)
115{
116 if(CLK->PWRCTL & CLK_PWRCTL_LXT_EN )
117 return __LXT;
118 else
119 return 0;
120}
121
127uint32_t CLK_GetHCLKFreq(void)
128{
130 return SystemCoreClock;
131}
132
138uint32_t CLK_GetPCLK0Freq(void)
139{
140 uint32_t Div[]= {1,2,4,8,16,1,1,1};
141 uint32_t PCLK_Div;
142 PCLK_Div = CLK->APBDIV & CLK_APBDIV_APB0DIV_Msk;
144 return SystemCoreClock/Div[PCLK_Div];
145}
146
152uint32_t CLK_GetPCLK1Freq(void)
153{
154 uint32_t Div[]= {1,2,4,8,16,1,1,1};
155 uint32_t PCLK_Div;
156 PCLK_Div = CLK->APBDIV & CLK_APBDIV_APB1DIV_Msk;
158 return SystemCoreClock/Div[PCLK_Div];
159}
160
166uint32_t CLK_GetCPUFreq(void)
167{
169 return SystemCoreClock;
170}
171
178{
179 uint32_t u32Freq =0, u32PLLSrc;
180 uint32_t u32SRC_N,u32PLL_M,u32PllReg;
181
182 u32PllReg = CLK->PLLCTL;
183
184 if (u32PllReg & CLK_PLLCTL_PD)
185 return 0; /* PLL is in power down mode */
186
188 {
189 /* PLL source clock from HXT */
190 u32PLLSrc = __HXT;
191 }
192 else if((u32PllReg & CLK_PLLCTL_PLLSRC_Msk) == CLK_PLLCTL_PLL_SRC_HIRC)
193 {
194 /* HIRC Source Selection */
195 if(CLK->CLKSEL0 & CLK_CLKSEL0_HIRCSEL_Msk)
196 {
197 /* Clock source from HIRC1 (36MHz) */
198 u32PLLSrc =__HIRC36M;
199 }
200 else
201 {
202 /* Clock source from HIRC0 (12MHz) */
203 if(CLK->PWRCTL & CLK_PWRCTL_HIRC0FSEL_Msk)
204 u32PLLSrc =__HIRC16M;
205 else
206 u32PLLSrc =__HIRC12M;
207 }
208 }
209 else
210 {
211 /* PLL source clock from MIRC (4MHz) */
212 u32PLLSrc =__MIRC;
213 }
214
215 u32SRC_N = (u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos;
216 u32PLL_M = (u32PllReg & CLK_PLLCTL_PLLMLP_Msk) >> CLK_PLLCTL_PLLMLP_Pos;
217
218 u32Freq = u32PLLSrc * u32PLL_M / (u32SRC_N+1);
219
220 return u32Freq;
221}
222
228uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
229{
230 if(CLK->PWRCTL & CLK_PWRCTL_HXT_EN)
232 else if(CLK->PWRCTL & (CLK_PWRCTL_HIRC0_EN | CLK_PWRCTL_HIRC1_EN))
234 else
236
239 return SystemCoreClock;
240}
241
257void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
258{
259 CLK->CLKDIV0 = (CLK->CLKDIV0 & ~CLK_CLKDIV0_HCLKDIV_Msk) | u32ClkDiv;
260 CLK->CLKSEL0 = (CLK->CLKSEL0 & ~(CLK_CLKSEL0_HIRCSEL_Msk | CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
262}
263
274void CLK_SetPCLK0(uint32_t u32ClkDiv)
275{
276 CLK->APBDIV = (CLK->APBDIV & ~CLK_APBDIV_APB0DIV_Msk) | u32ClkDiv;
277}
278
289void CLK_SetPCLK1(uint32_t u32ClkDiv)
290{
291 CLK->APBDIV = (CLK->APBDIV & ~CLK_APBDIV_APB1DIV_Msk) | u32ClkDiv;
292}
293
381void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
382{
383 uint32_t u32tmp=0,u32sel=0,u32div=0;
384
385 if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk)
386 {
387 u32div =(uint32_t)&CLK->CLKDIV0+((MODULE_CLKDIV(u32ModuleIdx))*4);
388 u32tmp = *(volatile uint32_t *)(u32div);
389 u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv;
390 *(volatile uint32_t *)(u32div) = u32tmp;
391 }
392
393 if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk)
394 {
395 u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4);
396 u32tmp = *(volatile uint32_t *)(u32sel);
397 u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc;
398 *(volatile uint32_t *)(u32sel) = u32tmp;
399 }
400}
401
413void CLK_EnableXtalRC(uint32_t u32ClkMask)
414{
415 CLK->PWRCTL |= u32ClkMask;
416}
417
429void CLK_DisableXtalRC(uint32_t u32ClkMask)
430{
431 CLK->PWRCTL &= ~u32ClkMask;
432}
433
465void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
466{
467 *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
468}
469
501void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
502{
503 *(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
504}
505
515uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
516{
517 uint32_t u32PllCr,u32PLL_N,u32PLL_M,u32PLLReg;
518 if ( u32PllFreq < FREQ_16MHZ)
519 u32PllFreq=FREQ_16MHZ;
520 else if(u32PllFreq > FREQ_36MHZ)
521 u32PllFreq=FREQ_36MHZ;
522
523 if(u32PllClkSrc == CLK_PLLCTL_PLL_SRC_HXT)
524 {
525 /* PLL source clock from HXT */
526 CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLL_SRC_HIRC);
527 u32PllCr = __HXT;
528 }
529 else if(u32PllClkSrc == CLK_PLLCTL_PLL_SRC_HIRC)
530 {
531 /* PLL source clock from HIRC */
532 CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLL_SRC_HIRC) | (CLK_PLLCTL_PLL_SRC_HIRC);
533
534 /* HIRC Source Selection */
535 if(CLK->CLKSEL0 & CLK_CLKSEL0_HIRCSEL_Msk)
536 {
537 /* Clock source from HIRC1 (36MHz) */
538 u32PllCr =__HIRC36M;
539 }
540 else
541 {
542 /* Clock source from HIRC0 (12MHz) */
543 if(CLK->PWRCTL & CLK_PWRCTL_HIRC0FSEL_Msk)
544 u32PllCr =__HIRC16M;
545 else
546 u32PllCr =__HIRC12M;
547 }
548 }
549 else
550 {
551 /* PLL source clock from MIRC (4MHz) */
552 CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLL_SRC_MIRC) | (CLK_PLLCTL_PLL_SRC_MIRC);
553 u32PllCr =__MIRC;
554 }
555
556 u32PLL_N=u32PllCr/1000000;
557 u32PLL_M=u32PllFreq/1000000;
558 while(1)
559 {
560 if(u32PLL_M<=48 && u32PLL_N<=36 ) break;
561 u32PLL_M >>=1;
562 u32PLL_N >>=1;
563 }
564 u32PLLReg = (u32PLL_M<<CLK_PLLCTL_PLLMLP_Pos) | ((u32PLL_N-1)<<CLK_PLLCTL_INDIV_Pos);
565 CLK->PLLCTL = ( CLK->PLLCTL & ~(CLK_PLLCTL_PLLMLP_Msk | CLK_PLLCTL_INDIV_Msk ) )| u32PLLReg;
566
567 if(u32PllClkSrc==CLK_PLLCTL_PLL_SRC_HIRC)
568 CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLLSRC_Msk) | (CLK_PLLCTL_PLL_SRC_HIRC);
569 else if(u32PllClkSrc==CLK_PLLCTL_PLL_SRC_HXT)
570 CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLLSRC_Msk) | (CLK_PLLCTL_PLL_SRC_HXT);
571 else
572 CLK->PLLCTL = (CLK->PLLCTL & ~CLK_PLLCTL_PLLSRC_Msk) | (CLK_PLLCTL_PLL_SRC_MIRC);
573
574 CLK->PLLCTL &= ~CLK_PLLCTL_PD_Msk;
575 return CLK_GetPLLClockFreq();
576}
577
584{
585 CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
586}
587
596void CLK_SysTickDelay(uint32_t us)
597{
598 SysTick->LOAD = us * CyclesPerUs;
599 SysTick->VAL = (0x00);
600 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
601
602 /* Waiting for down-count to zero */
603 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
604 SysTick->CTRL = 0;
605}
606
617void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
618{
619 SysTick->CTRL=0;
620 if( u32ClkSrc== CLK_CLKSEL0_STCLKSEL_HCLK ) /* Set System Tick clock source */
621 SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
622 else
623 {
624 SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
625 }
626 SysTick->LOAD = u32Count; /* Set System Tick reload value */
627 SysTick->VAL = 0; /* Clear System Tick current value and counter flag */
628 SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; /* Set System Tick counter enabled */
629}
630
637{
638 SysTick->CTRL = 0; /* Set System Tick counter disabled */
639}
640
657uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
658{
659 uint32_t u32TimeOutCnt = SystemCoreClock / 2;
660 uint32_t u32Ret = 1U;
661
663 while((CLK->STATUS & u32ClkMask) != u32ClkMask)
664 {
665 if(--u32TimeOutCnt == 0)
666 {
667 u32Ret = 0U;
668 break;
669 }
670 }
671
672 if(u32TimeOutCnt == 0)
674
675 return u32Ret;
676}
677
678 /* end of group NANO103_CLK_EXPORTED_FUNCTIONS */
680 /* end of group NANO103_CLK_Driver */
682 /* end of group NANO103_Device_Driver */
684
685/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
686
NANO103 peripheral access layer header file. This file contains all the peripheral register's definit...
int32_t g_CLK_i32ErrCode
Definition: clk.c:22
#define CLK_CLKSEL0_STCLKSEL_HCLK
Definition: clk.h:258
#define CLK_PLLCTL_PLL_SRC_HXT
Definition: clk.h:100
#define CLK_PWRCTL_HXT_EN
Definition: clk.h:38
#define CLK_PWRCTL_HIRC1_EN
Definition: clk.h:46
#define MODULE_NoMsk
Definition: clk.h:279
#define MODULE_CLKSEL_Msk(x)
Definition: clk.h:273
#define CLK_CLKSEL0_HCLKSEL_PLL
Definition: clk.h:140
#define FREQ_36MHZ
Definition: clk.h:34
#define CLK_PLLCTL_PLL_SRC_HIRC
Definition: clk.h:101
#define MODULE_CLKSEL_Pos(x)
Definition: clk.h:274
#define CLK_PLLCTL_PD
Definition: clk.h:99
#define CLK_HCLK_CLK_DIVIDER(x)
Definition: clk.h:246
#define MODULE_CLKDIV_Pos(x)
Definition: clk.h:277
#define MODULE_IP_EN_Pos(x)
Definition: clk.h:278
#define MODULE_CLKDIV_Msk(x)
Definition: clk.h:276
#define CLK_PWRCTL_LXT_EN
Definition: clk.h:39
#define CLK_PLLCTL_PLL_SRC_MIRC
Definition: clk.h:102
#define FREQ_16MHZ
Definition: clk.h:35
#define MODULE_CLKDIV(x)
Definition: clk.h:275
#define MODULE_APBCLK(x)
Definition: clk.h:271
#define CLK_PWRCTL_HIRC0_EN
Definition: clk.h:40
#define CLK_TIMEOUT_ERR
Definition: clk.h:321
#define MODULE_CLKSEL(x)
Definition: clk.h:272
void CLK_Idle(void)
This function let system enter to Idle mode.
Definition: clk.c:90
void CLK_SetPCLK0(uint32_t u32ClkDiv)
This function set APB PCLK0 clock divider.
Definition: clk.c:274
uint32_t CLK_GetHCLKFreq(void)
This function get HCLK frequency. The frequency unit is Hz.
Definition: clk.c:127
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
This function set PLL frequency.
Definition: clk.c:515
void CLK_DisableCKO(void)
This function disable frequency output function.
Definition: clk.c:33
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
This function enable module clock.
Definition: clk.c:465
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
This function enable frequency divider module clock, enable frequency divider clock function and conf...
Definition: clk.c:58
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
This function disable module clock.
Definition: clk.c:501
void CLK_SysTickDelay(uint32_t us)
This function execute delay function.
Definition: clk.c:596
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
This function check selected clock source status.
Definition: clk.c:657
uint32_t CLK_GetLXTFreq(void)
This function get external low frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:114
uint32_t CLK_GetPCLK1Freq(void)
This function get PCLK1 frequency. The frequency unit is Hz.
Definition: clk.c:152
void CLK_PowerDown(void)
This function let system enter to fractal fx-2-down mode.
Definition: clk.c:76
uint32_t CLK_GetPCLK0Freq(void)
This function get PCLK0 frequency. The frequency unit is Hz.
Definition: clk.c:138
void CLK_DisablePLL(void)
This function disable PLL.
Definition: clk.c:583
uint32_t CLK_GetCPUFreq(void)
This function get CPU frequency. The frequency unit is Hz.
Definition: clk.c:166
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set HCLK clock source and HCLK clock divider.
Definition: clk.c:257
void CLK_SetPCLK1(uint32_t u32ClkDiv)
This function set APB PCLK1 clock divider.
Definition: clk.c:289
void CLK_DisableXtalRC(uint32_t u32ClkMask)
This function disable clock source.
Definition: clk.c:429
void CLK_DisableSysTick(void)
Disable System Tick counter.
Definition: clk.c:636
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
This function set selected module clock source and module clock divider.
Definition: clk.c:381
void CLK_EnableXtalRC(uint32_t u32ClkMask)
This function enable clock source.
Definition: clk.c:413
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
Enable System Tick counter.
Definition: clk.c:617
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
This function set HCLK frequency. The frequency unit is Hz. The range of u32Hclk is 16 ~ 48 MHz.
Definition: clk.c:228
uint32_t CLK_GetPLLClockFreq(void)
This function get PLL frequency. The frequency unit is Hz.
Definition: clk.c:177
uint32_t CLK_GetHXTFreq(void)
This function get external high frequency crystal frequency. The frequency unit is Hz.
Definition: clk.c:101
#define CLK_PLLCTL_INDIV_Pos
Definition: Nano103.h:2885
#define CLK_PLLCTL_PLLSRC_Msk
Definition: Nano103.h:2895
#define CLK_STATUS_PLLSTB_Msk
Definition: Nano103.h:2775
#define CLK_PWRCTL_PDEN_Msk
Definition: Nano103.h:2673
#define CLK_APBDIV_APB0DIV_Msk
Definition: Nano103.h:2910
#define CLK_CLKOCTL_CLKOEN_Msk
Definition: Nano103.h:2901
#define CLK_PLLCTL_INDIV_Msk
Definition: Nano103.h:2886
#define CLK_CLKSEL0_HCLKSEL_Msk
Definition: Nano103.h:2793
#define CLK_PLLCTL_PD_Msk
Definition: Nano103.h:2892
#define CLK_PLLCTL_PLLMLP_Pos
Definition: Nano103.h:2882
#define CLK_PWRCTL_PDWKDLY_Msk
Definition: Nano103.h:2667
#define CLK_APBDIV_APB1DIV_Msk
Definition: Nano103.h:2913
#define CLK_APBCLK_CLKOCKEN_Msk
Definition: Nano103.h:2727
#define CLK_PWRCTL_HIRC0FSEL_Msk
Definition: Nano103.h:2682
#define CLK_CLKOCTL_DIV1EN_Pos
Definition: Nano103.h:2903
#define CLK_PLLCTL_PLLMLP_Msk
Definition: Nano103.h:2883
#define CLK_CLKSEL0_HIRCSEL_Msk
Definition: Nano103.h:2796
#define CLK
Pointer to CLK register structure.
Definition: Nano103.h:13802
#define __HXT
uint32_t CyclesPerUs
uint32_t SystemCoreClock
#define __HIRC16M
#define __LXT
#define __HIRC36M
#define __HIRC12M
void SystemCoreClockUpdate(void)
Updates the SystemCoreClock with current core Clock retrieved from CPU registers.
#define __MIRC