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NANO103 BSP V3.01.004
The Board Support Package for Nano103 Series
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NANO103 Device Specific Peripheral registers structures
#define INT_IRQ0_SRC_INT_SRC_Msk (0xful << INT_IRQ0_SRC_INT_SRC_Pos) |
INT_T::IRQ0_SRC: INT_SRC Mask
#define INT_IRQ0_SRC_INT_SRC_Pos (0) |
@addtogroup INT_CONST INT Bit Field Definition Constant Definitions for INT Controller
INT_T::IRQ0_SRC: INT_SRC Position
#define INT_IRQ10_SRC_INT_SRC_Msk (0xful << INT_IRQ10_SRC_INT_SRC_Pos) |
INT_T::IRQ10_SRC: INT_SRC Mask
#define INT_IRQ10_SRC_INT_SRC_Pos (0) |
INT_T::IRQ10_SRC: INT_SRC Position
#define INT_IRQ11_SRC_INT_SRC_Msk (0xful << INT_IRQ11_SRC_INT_SRC_Pos) |
INT_T::IRQ11_SRC: INT_SRC Mask
#define INT_IRQ11_SRC_INT_SRC_Pos (0) |
INT_T::IRQ11_SRC: INT_SRC Position
#define INT_IRQ12_SRC_INT_SRC_Msk (0xful << INT_IRQ12_SRC_INT_SRC_Pos) |
INT_T::IRQ12_SRC: INT_SRC Mask
#define INT_IRQ12_SRC_INT_SRC_Pos (0) |
INT_T::IRQ12_SRC: INT_SRC Position
#define INT_IRQ13_SRC_INT_SRC_Msk (0xful << INT_IRQ13_SRC_INT_SRC_Pos) |
INT_T::IRQ13_SRC: INT_SRC Mask
#define INT_IRQ13_SRC_INT_SRC_Pos (0) |
INT_T::IRQ13_SRC: INT_SRC Position
#define INT_IRQ14_SRC_INT_SRC_Msk (0xful << INT_IRQ14_SRC_INT_SRC_Pos) |
INT_T::IRQ14_SRC: INT_SRC Mask
#define INT_IRQ14_SRC_INT_SRC_Pos (0) |
INT_T::IRQ14_SRC: INT_SRC Position
#define INT_IRQ15_SRC_INT_SRC_Msk (0xful << INT_IRQ15_SRC_INT_SRC_Pos) |
INT_T::IRQ15_SRC: INT_SRC Mask
#define INT_IRQ15_SRC_INT_SRC_Pos (0) |
INT_T::IRQ15_SRC: INT_SRC Position
#define INT_IRQ16_SRC_INT_SRC_Msk (0xful << INT_IRQ16_SRC_INT_SRC_Pos) |
INT_T::IRQ16_SRC: INT_SRC Mask
#define INT_IRQ16_SRC_INT_SRC_Pos (0) |
INT_T::IRQ16_SRC: INT_SRC Position
#define INT_IRQ17_SRC_INT_SRC_Msk (0xful << INT_IRQ17_SRC_INT_SRC_Pos) |
INT_T::IRQ17_SRC: INT_SRC Mask
#define INT_IRQ17_SRC_INT_SRC_Pos (0) |
INT_T::IRQ17_SRC: INT_SRC Position
#define INT_IRQ18_SRC_INT_SRC_Msk (0xful << INT_IRQ18_SRC_INT_SRC_Pos) |
INT_T::IRQ18_SRC: INT_SRC Mask
#define INT_IRQ18_SRC_INT_SRC_Pos (0) |
INT_T::IRQ18_SRC: INT_SRC Position
#define INT_IRQ19_SRC_INT_SRC_Msk (0xful << INT_IRQ19_SRC_INT_SRC_Pos) |
INT_T::IRQ19_SRC: INT_SRC Mask
#define INT_IRQ19_SRC_INT_SRC_Pos (0) |
INT_T::IRQ19_SRC: INT_SRC Position
#define INT_IRQ1_SRC_INT_SRC_Msk (0xful << INT_IRQ1_SRC_INT_SRC_Pos) |
INT_T::IRQ1_SRC: INT_SRC Mask
#define INT_IRQ1_SRC_INT_SRC_Pos (0) |
INT_T::IRQ1_SRC: INT_SRC Position
#define INT_IRQ20_SRC_INT_SRC_Msk (0xful << INT_IRQ20_SRC_INT_SRC_Pos) |
INT_T::IRQ20_SRC: INT_SRC Mask
#define INT_IRQ20_SRC_INT_SRC_Pos (0) |
INT_T::IRQ20_SRC: INT_SRC Position
#define INT_IRQ21_SRC_INT_SRC_Msk (0xful << INT_IRQ21_SRC_INT_SRC_Pos) |
INT_T::IRQ21_SRC: INT_SRC Mask
#define INT_IRQ21_SRC_INT_SRC_Pos (0) |
INT_T::IRQ21_SRC: INT_SRC Position
#define INT_IRQ22_SRC_INT_SRC_Msk (0xful << INT_IRQ22_SRC_INT_SRC_Pos) |
INT_T::IRQ22_SRC: INT_SRC Mask
#define INT_IRQ22_SRC_INT_SRC_Pos (0) |
INT_T::IRQ22_SRC: INT_SRC Position
#define INT_IRQ23_SRC_INT_SRC_Msk (0xful << INT_IRQ23_SRC_INT_SRC_Pos) |
INT_T::IRQ23_SRC: INT_SRC Mask
#define INT_IRQ23_SRC_INT_SRC_Pos (0) |
INT_T::IRQ23_SRC: INT_SRC Position
#define INT_IRQ24_SRC_INT_SRC_Msk (0xful << INT_IRQ24_SRC_INT_SRC_Pos) |
INT_T::IRQ24_SRC: INT_SRC Mask
#define INT_IRQ24_SRC_INT_SRC_Pos (0) |
INT_T::IRQ24_SRC: INT_SRC Position
#define INT_IRQ25_SRC_INT_SRC_Msk (0xful << INT_IRQ25_SRC_INT_SRC_Pos) |
INT_T::IRQ25_SRC: INT_SRC Mask
#define INT_IRQ25_SRC_INT_SRC_Pos (0) |
INT_T::IRQ25_SRC: INT_SRC Position
#define INT_IRQ26_SRC_INT_SRC_Msk (0xful << INT_IRQ26_SRC_INT_SRC_Pos) |
INT_T::IRQ26_SRC: INT_SRC Mask
#define INT_IRQ26_SRC_INT_SRC_Pos (0) |
INT_T::IRQ26_SRC: INT_SRC Position
#define INT_IRQ27_SRC_INT_SRC_Msk (0xful << INT_IRQ27_SRC_INT_SRC_Pos) |
INT_T::IRQ27_SRC: INT_SRC Mask
#define INT_IRQ27_SRC_INT_SRC_Pos (0) |
INT_T::IRQ27_SRC: INT_SRC Position
#define INT_IRQ28_SRC_INT_SRC_Msk (0xful << INT_IRQ28_SRC_INT_SRC_Pos) |
INT_T::IRQ28_SRC: INT_SRC Mask
#define INT_IRQ28_SRC_INT_SRC_Pos (0) |
INT_T::IRQ28_SRC: INT_SRC Position
#define INT_IRQ29_SRC_INT_SRC_Msk (0xful << INT_IRQ29_SRC_INT_SRC_Pos) |
INT_T::IRQ29_SRC: INT_SRC Mask
#define INT_IRQ29_SRC_INT_SRC_Pos (0) |
INT_T::IRQ29_SRC: INT_SRC Position
#define INT_IRQ2_SRC_INT_SRC_Msk (0xful << INT_IRQ2_SRC_INT_SRC_Pos) |
INT_T::IRQ2_SRC: INT_SRC Mask
#define INT_IRQ2_SRC_INT_SRC_Pos (0) |
INT_T::IRQ2_SRC: INT_SRC Position
#define INT_IRQ30_SRC_INT_SRC_Msk (0xful << INT_IRQ30_SRC_INT_SRC_Pos) |
INT_T::IRQ30_SRC: INT_SRC Mask
#define INT_IRQ30_SRC_INT_SRC_Pos (0) |
INT_T::IRQ30_SRC: INT_SRC Position
#define INT_IRQ31_SRC_INT_SRC_Msk (0xful << INT_IRQ31_SRC_INT_SRC_Pos) |
INT_T::IRQ31_SRC: INT_SRC Mask
#define INT_IRQ31_SRC_INT_SRC_Pos (0) |
INT_T::IRQ31_SRC: INT_SRC Position
#define INT_IRQ3_SRC_INT_SRC_Msk (0xful << INT_IRQ3_SRC_INT_SRC_Pos) |
INT_T::IRQ3_SRC: INT_SRC Mask
#define INT_IRQ3_SRC_INT_SRC_Pos (0) |
INT_T::IRQ3_SRC: INT_SRC Position
#define INT_IRQ4_SRC_INT_SRC_Msk (0xful << INT_IRQ4_SRC_INT_SRC_Pos) |
INT_T::IRQ4_SRC: INT_SRC Mask
#define INT_IRQ4_SRC_INT_SRC_Pos (0) |
INT_T::IRQ4_SRC: INT_SRC Position
#define INT_IRQ5_SRC_INT_SRC_Msk (0xful << INT_IRQ5_SRC_INT_SRC_Pos) |
INT_T::IRQ5_SRC: INT_SRC Mask
#define INT_IRQ5_SRC_INT_SRC_Pos (0) |
INT_T::IRQ5_SRC: INT_SRC Position
#define INT_IRQ6_SRC_INT_SRC_Msk (0xful << INT_IRQ6_SRC6_INT_SRC_Pos) |
INT_T::IRQ6_SRC: INT_SRC Mask
#define INT_IRQ6_SRC_INT_SRC_Pos (0) |
INT_T::IRQ6_SRC: INT_SRC Position
#define INT_IRQ7_SRC_INT_SRC_Msk (0xful << INT_IRQ7_SRC_INT_SRC_Pos) |
INT_T::IRQ7_SRC: INT_SRC Mask
#define INT_IRQ7_SRC_INT_SRC_Pos (0) |
INT_T::IRQ7_SRC: INT_SRC Position
#define INT_IRQ8_SRC_INT_SRC_Msk (0xful << INT_IRQ8_SRC_INT_SRC_Pos) |
INT_T::IRQ8_SRC: INT_SRC Mask
#define INT_IRQ8_SRC_INT_SRC_Pos (0) |
INT_T::IRQ8_SRC: INT_SRC Position
#define INT_IRQ9_SRC_INT_SRC_Msk (0xful << INT_IRQ9_SRC_INT_SRC_Pos) |
INT_T::IRQ9_SRC: INT_SRC Mask
#define INT_IRQ9_SRC_INT_SRC_Pos (0) |
INT_T::IRQ9_SRC: INT_SRC Position
#define INT_MCU_IRQ_MCU_IRQ_Msk (0xfffffffful << INT_MCU_IRQ_MCU_IRQ_Pos) |
INT_T::MCU_IRQ: MCU_IRQ Mask
#define INT_MCU_IRQ_MCU_IRQ_Pos (0) |
INT_T::MCU_IRQ: MCU_IRQ Position
#define INT_NMI_SEL_NMI_SEL_Msk (0x1ful << INT_NMI_SEL_NMI_SEL_Pos) |
INT_T::NMI_SEL: NMI_SEL Mask
#define INT_NMI_SEL_NMI_SEL_Pos (0) |
INT_T::NMI_SEL: NMI_SEL Position